Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-02
2009-02-24
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07496867
ABSTRACT:
A method of managing a cell library regarding power optimization is disclosed. The method generally includes the steps of (A) reading a plurality of first modules within a first region of a circuit design stored in a design file, (B) calculating a first merit value indicating a relative sensitivity of the first region to a power consumption, the first merit value having a range from a static power dominated value to a dynamic power dominated value and (C) creating a constraint file configured to limit a design tool to a first subset of a plurality of replacement modules based on the first merit value such that the design tool automatically optimizes the power consumption of the first region by replacing at least one of the first modules with at least one of the replacement modules within the first subset, the replacement modules residing in a library file.
REFERENCES:
patent: 5692160 (1997-11-01), Sarin
patent: 7114134 (2006-09-01), Zhang et al.
patent: 2005/0278659 (2005-12-01), Zhang et al.
Brown Jeffrey S.
Byrn Jonathan W.
Turner Mark F.
Garbowski Leigh Marie
LSI Corporation
Maiorana PC Christopher P.
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