Cell-layout method in integrated circuit devices

Details Cell-layout method in integrated circuit devices Cell-layout method in integrated circuit devices

2000-01-28

2002-10-08

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06463575

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of a cell-layout in an integrated circuit device, and more particularly, relates to a method of a cell-layout according to a Min-Cut layout method.
2. Description of the Prior Art
In a layout method, so-called a Min-Cut layout method, the following processes are repeated hierarchically to position cell-layouts: among a plurality of segments, called cut lines, established on a chip, one segment is selected, and a region on a chip is divided into two by the selected segment, and then cells are assigned (1) to reduce the number of nets (number of cuts) intersected with the cut lines as can be done, and (2) to equalize cell densities in two small regions generated by a division of the region on the chip into two by the cut line. The cell density here defines a ratio of the sum of cell areas assigned in a cell-layout region to cell areas allocable therein.
FIG. 11
is a flow chart showing a method of a cell-layout in an integrated circuit device according to a conventional Min-Cut method. In the drawing, ST
1
designates a step of establishing a plurality of segments (hereinafter, referred to as “cut lines”) which divides an integrated circuit substrate (hereinafter, referred to as “substrate”) in vertical and horizontal directions, ST
2
designates a step of assigning all the unplaced cells in the circuit in an entire substrate to be assumed as one cell-layout region, ST
4
designates a step of determining a cut-line direction to be next processed in accordance with a predetermined turn, ST
5
designates a step of distinguishing a division direction in accordance with the direction determined in the step ST
4
to branch the process, ST
6
and ST
7
designate steps of selecting one cut line per row line and one cut line per column line in the cell-layout region on the substrate among non-processed cut lines in the horizontal and vertical directions, respectively, depending on the direction determined in the step ST
4
, ST
33
denotes a step for processing a Min-Cut division on a single CPU with respect to the cut line selected in the step ST
6
or ST
7
one by one, ST
9
designates a step of marking “processed” for the cut line selected in the step ST
6
or ST
7
and renewing cell-layout region information, and ST
19
designates a step of distinguishing whether or not the processes have been completed with respect to all the cut lines. The steps ST
4
, ST
5
, ST
6
or ST
7
, ST
33
, ST
9
, ST
19
will be repeated in this order until a distinction that the processes have been completed with respect to all the cut lines in the step ST
19
.
The Min-Cut division is defined that after a cell-layout region intersected with a cut line is divided into two cell-layout regions by the cut line, the cells assigned at the cell-layout region before the division is transferred to the cell-layout region after the division so as to minimize the number of signal lines intersected with the cut lines and to equalize cell densities in the cell-layout regions after the division.
Next,
FIGS. 3
,
4
,
12
-
14
are views for an operational explanation related to a conventional method of a cell-layout in an integrated circuit device. In the drawings, reference numerals
21
a
-
21
g
denote peripheral input/output cells,
22
a
-
22
l
denote cells to be placed,
23
a
-
23
u
denote signal lines,
24
a
-
24
d
denote logic hierarchy blocks,
25
denotes a substrate,
26
a
-
26
p
denote slots for placing the peripheral input/output cells,
27
a
-
27
p
denote slots for placing the cells,
28
denotes a wire grid designating a position where wires are passable,
29
a
-
29
f
denote cut lines for the Min-Cut division process,
31
a
-
31
f
denote cell-layout regions generated by the division, and
32
a
-
32
s
denote wiring patterns.
Any one of the peripheral input/output cells
21
a
-
21
g
may be placed on the slots
26
a
-
26
p
. The layouts of the peripheral input/output cells are already determined herein, and the peripheral input/output cells
21
a
-
21
g
are allocated at the slots
26
a
,
26
c
,
26
f
,
26
g
,
26
n
,
26
k
,
26
i
, respectively. Anyone of the cells
22
a
-
22
l
may be placed at the inner slots
27
a
-
27
p
. During a wiring process after the cell-layouts, the wiring patterns may be only passable for parts which are not blocked by the cells or other wires on the wire grids
28
.
Referring to the flow chart in
FIG. 11
, the operation will be next described when the integrated circuit shown in
FIG. 3
is placed on the substrate shown in FIG.
4
.
In the step ST
1
of
FIG. 11
, the cut lines
29
a
-
29
f
for dividing the substrate
25
are established. It is here designed that in order to determine the cell-layouts after the divisions have been completed by all the cut lines, only one of the slots is contained in a field enclosed by the cut lines. It is assumed that alternate processes of horizontal and vertical divisions are predetermined with respect to the cut lines
29
a
-
29
f
. All the cells
22
a
-
22
l
are assigned as the entire substrate is considered as one cell-layout region in the step ST
2
. Since an implementation of the horizontal division is determined in the step ST
4
, the process flow branches to the step ST
6
in the step ST
5
. The cut line
29
e
which divides the cell-layout region on the substrate is selected in the step ST
6
. The Min-Cut division is implemented by the cut line
29
e
in the step ST
33
.
The cells are here assigned in order to minimize the number of the signal lines intersected with the cut line
29
e
and to equalize cell densities in the two regions produced by the division. In this manner, as shown in
FIG. 12
, the two cell-layout regions
31
a
,
31
b
are created: in one of these regions, six cells of the cells
22
a
-
22
f
are assigned on the upper side of the cut line
29
e
, i.e., on the side of the cell-layout region
31
a
, while in the other thereof, the remaining cells
22
g
-
22
l
are assigned on the lower side of the cut line
29
e
, i.e., on the side of the cell-layout region
31
b
. In this situation, the signal lines
23
g
,
23
i
,
23
m
intersect with the cut line, and the number of the cuts becomes three. After a determination of the cell assignment, the mark “division-processed” is prepared for the cut line
29
e
in the step ST
9
, and the cell-layout region information is renewed in accordance with the above division-results.
At this point of time, the division by the cut line
29
e
is completed, the cell-layout region
31
a
assigned by the cells
22
a
-
22
f
, and the cell-layout region
31
b
assigned by the cells
22
g
-
22
l
are present on the substrate
25
. In the next step ST
19
, the process flow goes back to the step ST
4
due to the remaining non-processed cut lines. In the step ST
4
, an implementation of the vertical division is determined. Thus in the step ST
7
, the cut line
29
b
is selected, which divides the cell-layout regions
31
a
,
31
b
on the substrate
25
vertically.
Then, the steps ST
33
, ST
9
are implemented with respect to the cut line
29
b
as well as the cut line
29
e
, and the division with respect to the cut line
29
b
is completed. As a result, as shown in
FIG. 13
, the cell-layout region
31
c
including the cells
22
a
,
22
b
,
22
d
, the cell-layout region
31
d
including the cells
22
g
,
22
i
,
22
j
, the cell-layout region
3
l
e
including the cells
22
c
,
22
e
,
22
f
, and the cell-layout region
31
f
including the cells
22
h
,
22
k
,
22
l
come to exist on the substrate
25
.
Thereafter, the same divisions as the aforementioned cut lines
29
e
,
29
b
are implemented with respect to the cut lines
29
d
,
29
f
and the cut lines
29
a
,
29
c
in
FIG. 4
, respectively, until completion of the processes with respect to all the cut lines is distinguished in the step ST
19
. In these process steps, in the step ST
6
the cut lines
29
d
,
29
f
are selected, and in the step ST
7
the cut lines
29
a
,
29
c
are selected, while in the step ST
33
the di

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