Cell density improvement in planar DMOS with farther-spaced body

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257339, 257329, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

058941509

ABSTRACT:
This invention discloses a DMOS planar power device having a plurality of transistor cells formed in a semiconductor substrate with a drain region of a first conductivity type disposed at a bottom surface of the substrate. Each of the DMOS transistor cells includes a polysilicon segment constituting a gate supported on a top surface of the substrate wherein the gate being disposed substantially in a center portion of the transistor cell. The DMOS transistor cell further includes a source region of the first conductivity type disposed in the substrate surrounding edges of the gate with a portion extends underneath the gate. The DMOS transistor cell further includes a body region doped with a body dopant of a second conductivity type disposed in the substrate encompassing the source region. The body region has a portion extending underneath the gate having a under-the-gate distance less than a lateral diffusion of the body dopant and the body region having outer edges extending outwardly to neighboring transistor cells. The DMOS transistor cell further includes a shallow low-concentration first-conductivity-type region under the gate wherein the shallow low-concentration first-conductivity-type region having a depth shallower than a depth of the source region.

REFERENCES:
patent: 4972240 (1990-11-01), Murakami et al.
patent: 5479037 (1995-12-01), Hshieh

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