Cell buffering system with priority cache in an ATM system

Details Cell buffering system with priority cache in an ATM system Cell buffering system with priority cache in an ATM system

2005-07-05

2005-07-05

Portka, Gary (Department: 2188)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

C711S151000, C710S039000, C710S055000

Reexamination Certificate

active

06915360

ABSTRACT:
The present invention provides an apparatus and system for buffering data in a communication network with an arranged priority which enables traffic shaping. A cell buffer unit (600) is arranged with a plurality of queues (614) configured to store PDUs on-chip and off-chip. There are associated queues both on-chip and off-chip for each priority queue. A cell buffer controller (620) forwards PDUs to a predetermined priority queue and manages the transfer of PDUs off-chip when a priority queue on-chip is fully occupied. The controller (620) also manages the transfer of PDUs from the off-chip queue when the on-chip priority queue becomes less than fully occupied.

REFERENCES:
patent: 6401145 (2002-06-01), Baskey et al.
patent: 6453394 (2002-09-01), Miki et al.
patent: 6487210 (2002-11-01), Janoska et al.
patent: 6539024 (2003-03-01), Janoska et al.
patent: 6681270 (2004-01-01), Agarwala et al.

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