Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-19
2002-05-28
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06397372
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of integrated circuits (IC). More specifically, the present invention relates to methods and apparatuses associated with processing an IC design.
2. Background Information
Because of the ever increasing complexity of IC designs, most modern IC designs are expressed in terms of hierarchically organized design cells. For example, an exemplary IC may be expressed in terms of a collection of placements of design cells A, B, C, . . . and various “interconnecting” geometric elements, whereas design cell A may in turn be likewise expressed as a collection of placements of design cells Al, A
2
, . . . , and various “interconnecting” geometric elements within cell A, design cell B expressed as a collection of placements of design cells B
1
, B
2
, . . . , and various “interconnecting” geometric elements within cell B, and so forth.
Additionally, prior to fabrication (especially those IC designs fabricated using sub-micron processes), various verification operations, including but not limited to design rule checks (such as spacing), RC analysis, and so forth, are performed to ensure the fabricated IC will function as designed. In order to verify a particular design cell, in view of the hierarchical nature of its organization, it is necessary to verify the context independent and context dependent portions of the design cell separately. The context dependent portion of the design cell is promoted upward recursively until it is a part of the context independent portion of a higher level design cell. A process known as “selective promotion”.
In order to facilitate efficient performance of these operations, various design cells injection techniques are employed to reduce the amount of selective promotions. Design cells injection is a process by which a design cell is re-expressed in terms of a number of artificially created design cells. For examples, a design cell A having placements of design cells A
1
, A
2
, A
3
, A
4
and A
5
may be re-expressed in terms of placements of artificially created design cells A
10
and A
11
, where artificially created design cell A
10
is comprised of placements of design cells A
1
and A
2
, and artificially created design cell A
11
is comprised of placements of design cells A
3
, A
4
and A
5
. A particular “placement based” design cell injection technique is the subject of co-pending U.S. patent application Ser. No. 09/234,030, entitled “Placement Based Design Cell Injection Into An Integrated Circuit Design”, filed contemporaneously. Three other prior art design cell injection techniques are also described in the background section of the '030 patent application.
However, even with reduced selective promotion and employing some of the most powerful workstations known today, it is not uncommon for many of today's IC designs taking a day or two to be verified. The situation is expected to get worse as the complexity of IC designs continues to increase. Thus, additional techniques to further speed up the verification process is desired.
SUMMARY OF THE INVENTION
An EDA tool is provided with the ability to determine a cell based parallel verification order for a plurality of hierarchically organized design cells of an integrated circuit design, and the ability to verify the design cells in accordance with the cell based parallel verification order, with at least some of the design cells being verified in parallel. In one embodiment, the EDA tool is also provided with the ability to re-express a design cell of the IC design in terms of a number of newly formed intervening constituent design cells, with the new intervening constituent design cells being formed in accordance with a number of metrics profiling placements of original constituent design cells of the design cell.
REFERENCES:
patent: 5497334 (1996-03-01), Russell
patent: 6113647 (2000-05-01), Silve
Bozkus Zeki
Grodd Laurence W.
LandOfFree
Cell based parallel verification of an integrated circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cell based parallel verification of an integrated circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cell based parallel verification of an integrated circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2899624