Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-17
2002-12-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06493853
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to methods for designing and fabricating digital circuits, and in particular to simulation and analysis of the circuit design in order to detect and eliminate crosstalk induced by capacitive coupling.
BACKGROUND OF THE INVENTION
Before an integrated circuit is fabricated, a trial design is first analyzed by simulating the operation of the proposed circuits that are to be included within the integrated circuit. Simulation is used to verify correct functional operation of the circuit, as well as to verify correct dynamic timing operation. When two signal lines on an integrated circuit are physically adjacent there is a capacitance between the signal lines that may cause signal interference due to signal coupling.
Signal integrity is one of the key challenges in design and test, now and beyond 100 nm technologies. Rapid technology scaling is causing increased coupling capacitances due to reduced signal to signal spacing and increased distance from the substrate. Among several types of noise, crosstalk noise introduced due to parasitic coupling is predominant in digital designs. Interconnect parasitic coupling has two effects, at least. A first effect is on the delay due to different switching patterns and this affects the performance of the chip besides potential race conditions. A second effect is induced glitches or noise that could cause functional failure by switching logic-states. In the case of designs employing dynamic logic design styles, this problem is more severe due to increased noise sensitivities of pre-charged nodes. In the case of static logic, except for asynchronous signals such as preset/clear and clock nodes, a failure could result only when data inputs connected to storage elements are latched during the active phase of the clock.
Design complexities are increasing with system on chip (SOC) designs and increased length of interconnect at full-chip level is one of the major sources of crosstalk noise problem. This refers to integration of system level functions, for example, many functions in a cellular telephone integrated into one integrated circuit (IC). Typically, SOC designs have CPU cores, memory blocks, logic blocks and possibly analog design blocks, all on one chip. Dynamic simulation of large designs with millions of parasitics is computationally prohibitive; in order reduce computational loads, static noise verification is used. Magnitude of the parasitic coupling, behavior of victim drivers during noise injection and dependency between factors like timing and parasitic coupling are some of key challenges in noise verification.
A commonly used simulator for designing integrated circuits is SPICE, which is available from the University of California at Berkeley, via the Department of Electrical Engineering and Computer Sciences. However, a SPICE simulation of all the nets in an entire chip is far too complex to be practical.
In order to perform a SPICE simulation of a circuit, all of the nodes between every component in the circuit need to be numbered. Then those nodes, the type of components at each node, and the component magnitudes are entered into the SPICE program.
If the circuit which is being simulated is an entire integrated circuit chip, then the number of nodes and corresponding components which need to be entered into the SPICE program is overwhelming. Firstly, the number of nets may be 40,000 in a current typical integrated circuit design. Secondly, for each such net, about seventy discreet components need to be entered because in the actual chip, the net components are distributed. Specifically, each signal line has capacitance which is distributed throughout the line; and each signal line also has a resistance which is distributed throughout the line. To simulate these distributed components, each signal line needs to be represented by a RC ladder circuit which has about two dozen nodes; with each node having a resistor to the next node, a capacitor to ground, and a capacitor to any adjacent signal line.
After all of the nodes and corresponding components for all the nets are entered into the SPICE program, the program operates to determine the voltages which occur on each node in sequential increments of time. Typically, about 1,000 increments of ten picoseconds each are needed to obtain the entire voltage waveform on a node in one net in an integrated circuit chip. To determine the voltages for just one time increment the SPICE program repetitively solves a matrix equation which is of the form [Y][V]=[I]. Here, Y is an n-×-n matrix, V is an n×1 matrix, and I is an n×1 matrix; where n is the number of nodes in the circuit. Thus, for a single victim net with twenty aggressor nets, n is (24 nodes per net)×(21 nets) or 504.
For each increment in time the SPICE program makes about five iterations before it converges on a solution. This iterative process is repeated for each of the subsequent time increments. Using a current state of the art workstation, it takes about ten minutes to perform a SPICE simulation of a single circuit which has 500 nodes and for which a solution is sought for 1,000 time increments. Such a circuit represents a typical victim net with twenty aggressor nets. Consequently, to simulate a chip which has 40,000 nets would take about 400,000 minutes, or more than 270 days to complete!
Accordingly, a primary object of the present invention is to provide a method of designing circuit chips by which the above problems are overcome.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
SUMMARY OF THE INVENTION
A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic. Other instantiations of the cell are evaluated using the same multi-dimensional noise table. A prediction of whether each instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic associated with each instantiation of the cell.
In another form of the invention, an integrated circuit is fabricated according to a modified trial layout.
In another form of the invention, a computer system is provided which as a mass storage device that holds a design program for designing an integrated circuit according to the above described method.
REFERENCES:
patent: 5535133 (1996-07-01), Petschauer et al.
patent: 6449753 (2002-09-01), Aingaran et al.
Vittal, A. et al. “Modeling crosstalk in resistive VLSI interconnections”, IEEE, VLSI Design, 1999, pp. 470-475.
Apostol John
Hill Anthony M.
Savithri Nagaraj N.
Bowers Brandon
Brady III W. James
Laws Gerald E.
Siek Vuthe
Telecky , Jr. Frederick J.
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