Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-06-30
2001-01-23
Picard, Leo P. (Department: 2835)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S206000, C257S207000, C257S208000, C257S211000
Reexamination Certificate
active
06177709
ABSTRACT:
FIELD OF THE INVENTION
This application relates to designs for cell based arrays, and particularly relates to low power, high density designs for cell based arrays.
BACKGROUND OF THE INVENTION
The use of gate arrays and standard cells has become well known as an effective and efficient method for rapidly developing new semiconductor products substantial complexity. Such standard cells are typically used in cell-based arrays, and have wide application within the industry. A widely-accepted design for a gate array architecture that provides standard cell type densities is based on the design described in U.S. Pat. No. 5,289,021, commonly assigned to the assignee of the present invention and incorporated herein by reference.
However, despite the many advantages offered by cell based arrays, prior art designs cells have suffered from some limitations which have become more apparent as line widths have been reduced and complexity has increased. In particular, the typical prior art standard cell has been limited to a relatively low ratio between compute and drive cells. In particular, prior art designs have limited the ratio between compute and drive cells to no more than three- or four-to-one. Moreover, manufacturing limitations have served to impose a fixed, three-to-one limitation on most if not all prior art designs. Although the three-to-one ratio has enabled efficient construction of a great many circuits, and is particularly well suited to many high performance designs, there remain other applications—for example, low power applications—which could benefit from a ratio of compute to drive cells other than (and typically greater than) three-to-one.
As a result, there has been a need to develop a cell based array design which permits the implementation of larger, and in some instances unlimited, ratios of compute to drive cells.
SUMMARY OF THE INVENTION
The present invention substantially overcomes the limitations of the prior art by providing an extremely compact cell based array which permits high density, low power designs, including permitting designs implementing a virtually unlimited range of ratios between compute and drive cells. In particular, the present invention involves providing design flexibility to permit the ratio of compute cells to drive cells to be design dependent, and therefor optimized for each particular design. Because of the substantially larger size of the drive cell transistors compared to the compute cell transistors, increasing ratios of compute to drive cells offers significant reduction in power consumption, among other benefits. Further, higher densities can result for designs with high C/D ratios.
The cell based array of the present invention involves a new and novel cell structure which involves rearrangement of the compute cells relative to each other and to any associated drive cells, with the objectives of providing, among other things, lower power, higher density operation with greater optimization. To achieve these goals, an exemplary embodiment of the present invention includes adding a substrate tap to the compute cell and arranging adjacent compute cells to permit the substrate tap to be shared between adjacent compute cells. Further, although optional, the n-well taps preferably abut between adjacent compute cells.
In contrast to the compute cells, however, in at least some embodiments the well and substrate taps are preferably removed from the drive cell. Still further, in at least a presently preferred embodiment the source/drain areas of the transistors for adjacent drive cells is separated, thereby improving routability by providing an extra routing track between the drive cells.
Still further, additional performance gains may be provided by, in at least some embodiments, adding additional polysilicon heads to the drive cell while at the same time minimizing the number of bent gates to effectively increase channel width of the drive cell's PMOS device.
The invention is particularly well-suited to complex integrated circuits such cell-based arrays, but may be successfully implemented in a wide variety of circuit designs. Although the invention is explained in the context of a cell-based ray, it is to be understood that such an embodiment is exemplary only and not limiting.
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Duong Hung Van
Eakin James E.
McDermott & Will & Emery
Picard Leo P.
Synopsys Inc.
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