Cell array pattern layout for EEPROM device

Details Cell array pattern layout for EEPROM device Cell array pattern layout for EEPROM device

1991-05-21

1992-04-14

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365210, G11C 702, G11C 1134

Patent

active

051053853

ABSTRACT:
A memory cell array includes data storing memory cells which are arranged in a matrix form of m rows.times.n columns. The data storing memory cells are selected by means of m word lines and n bit lines. Dummy capacitance cells are arranged on the (n+1)th column of the memory cell array, and are connected to the word lines. The dummy capacitance cells are each formed of a transistor which has the same construction as a field transistor having a gate electrode formed of a polysilicon layer or the data storing memory cell and whose source is set in the electrically floating condition. Array edge memory cells are arranged on the (m+1)th row of the memory cell array, and are connected to n bit lines. The array edge memory cells have no influence on the circuit operation. A dummy memory cell is arranged in an intersecting position of the (m+1)th row and the (n+1)th column. A dummy bit line is connected to the dummy capacitance cells and dummy memory cell, and a dummy word line is connected to the array edge memory cell and dummy memory cell.

REFERENCES:
patent: 4094008 (1978-06-01), Lockwood et al.
patent: 4314360 (1982-02-01), Higuchi et al.
patent: 4371956 (1983-02-01), Maeda et al.
patent: 4622737 (1986-11-01), Ravaglia
patent: 4668970 (1987-03-01), Yatsuda et al.
patent: 4819212 (1989-04-01), Nakai et al.
patent: 4894802 (1990-01-01), Hsia et al.

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