Cell arrangement method for designing semiconductor...

Details Cell arrangement method for designing semiconductor... Cell arrangement method for designing semiconductor...

2007-05-18

2010-12-28

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07861202

ABSTRACT:
Logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit between flip-flops are defined is input. The logic circuit information is analyzed to detect a logic circuit sandwiched by two flip-flops. The number of logic stages of the detected logic circuit is counted. It is determined, according to the counted number of logic stages, to which substrate potential a cell used for the logic circuit is to be connected.

REFERENCES:
patent: 6308305 (2001-10-01), Sugiyama et al.
patent: 6823501 (2004-11-01), Dahl
patent: 6859917 (2005-02-01), Shimazaki et al.
patent: 7117469 (2006-10-01), Dahl
patent: 2002/0079927 (2002-06-01), Katoh et al.
patent: 2004/0025135 (2004-02-01), Hart et al.
patent: 2005/0280437 (2005-12-01), Lewis et al.
patent: 11-068045 (1999-03-01), None
Kuroda et al., “A High-Speed Low-Power 0.3μm CMOS Gate Array with Variable Threshold Voltage (VT) Scheme,” Semiconductor Device Engineering Laboratory, Toshiba Corp., IEEE, 1996, Kawasaki, Japan.

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