Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2002-06-06
2003-06-17
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S039000, C326S041000
Reexamination Certificate
active
06580289
ABSTRACT:
BACKGROUND
For many years, gate arrays have been used to provide quick-turnaround, low non-recurring-expense (NRE) semiconductor devices that are used for a variety of purposes. Traditionally, semiconductor wafers are processed up to but not including the first (bottom) metal layer, and then the wafers are saved in inventory. When a customer orders a semiconductor device to be fabricated for a specific application (an application specific integrated circuit or “ASIC”), the customer only has to pay for the masks that are required to configure the metal layers, but not for the transistor layers below. Thus, NRE is reduced. The wafers may be completed quickly, since only the metal layers remain to be fabricated, which also reduces the turn-around time that is necessary to build the device.
Recently more and more layers of metal have been incorporated into gate array semiconductor devices. Rather than two or three layers of metal, six to eight layers of metal are now common. As a result, gate arrays are no longer very low NRE, or provide quick-turnaround times. In order to regain the advantages of earlier gate arrays, several vendors have developed logic arrays, consisting of multiple, substantially identical logic cells, that may be configured for an application with either fewer or cheaper masks. In the case of fewer masks, the total number of metal layers and hence masks used to create the finished device often does not change. Rather, only a reduced subset of the total number of metal layers in a finished device are used to impart the custom configuration to the device. For example, so-called “one-mask” devices, in which only a single metal layer and hence a single mask imparts customization, may reduce both NRE and the turnaround-time.
An ASIC is a semiconductor device that combines large numbers of programmable blocks of logic circuits into a logic cell to create a device that is specifically adapted for a particular application, but at a cost that is lower than that of developing a completely new device from scratch. Like most integrated circuit chips, ASIC chips are manufactured using a lithographic process that depends on having a mask for each layer of the chip. In the case of a completely new chip, many unique masks may be required. In the case of an ASIC such as a gate array, however, some masks are generic, that is, the same for each different type of ASIC of a given programmable architecture, regardless of the application, while some are custom. It is the custom masks that impart the application specificity to the chip by programming the logic cells during the manufacturing process. Multiple custom masks may be required to accomplish the programming of an ASIC. The number depends to some extent on the design of the programmable cells. Although the number of custom masks required is less than the total number of masks, and certainly less than the number of masks required to create a completely new chip from scratch, each custom mask represents a significant cost in both money and development time.
In many cases, the cell architecture of an ASIC may be designed to reduce the number of custom masks that may be required to just one mask, which provides a significant cost and time savings. A “one mask” device allows all of the masks to remain generic except for a single mask, thus allowing the semiconductor manufacturer to invest in the generic or base masks just one time. Various designs may be implemented by customizing just a single mask instead of a complete mask set.
SUMMARY
The present invention provides for a semiconductor device and a method of testing the device having a plurality of logic cells interconnected using vias to connect routing tracks that are disposed among a plurality of layers in the device. The logic cells in the device include at least two three-input look-up tables, one two-input look-up table and a flip-flop. The components in the logic cell are connected so that any look-up table can drive at least one in-put of any other look-up table and where the flip-flop is connected to the lookup tables so that any look-up table can drive an input of the flip-flop.
In some embodiments, the semiconductor device may be designed to be configured or customized using less than the actual number of metal (including via) layer masks that will actually be used to create a final device. In some cases, this configuration will be accomplished with a single metal layer mask, which may be either a mask designed to create a layer of actual metal traces, or a layer of vias which move signals between metal layers.
In any case, a completed device is made by first forming the semiconductor layer where cells contain mask-configurable gate array as described above. Then, the plurality of metal layers are formed on top of the semiconductor layer for routing connections. At least some of the plurality of metal layers are customized and may be used to configure the device for a specific application.
REFERENCES:
patent: 5068603 (1991-11-01), Mahoney
patent: 5815726 (1998-09-01), Cliff
patent: 5898318 (1999-04-01), Pedersen
patent: 5905385 (1999-05-01), Sharpe-Geisler
patent: 5999015 (1999-12-01), Cliff et al.
patent: 6014038 (2000-01-01), How et al.
patent: 6194912 (2001-02-01), Or-Bach
patent: 6236229 (2001-05-01), Or-Bach
patent: 6245634 (2001-06-01), Or-Bach
patent: 6294927 (2001-09-01), Yoeli et al.
patent: 6331733 (2001-12-01), Or-Bach et al.
patent: 6331789 (2001-12-01), Or-Bach
patent: 6331790 (2001-12-01), Or-Bach et al.
Evans Charles L.
Moore & Van Allen PLLC
Tan Vibol
Tokar Michael
Viasic, Inc.
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