Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-10-04
2004-06-01
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S746000, C710S052000, C369S047100
Reexamination Certificate
active
06745349
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a CD-ROM decoder, and more particularly, to a CD-ROM decoder that corrects a code error contained in digital data and transfers the corrected digital data to a computer.
When a computer acquires digital data recorded on a recording medium, decode processing for correcting a code error contained in the digital data is executed using a drive system such as a CD-ROM system. Since the decode processing is executed in units of sectors that consist of a predetermined number of bytes, the digital data is buffered in a memory in units of sectors.
FIG. 1
is a schematic block diagram of a CD-ROM system
100
. Digital data that conforms to a predetermined format is recorded on a disk
1
along a recording track drawn in a spiral shape. The disk
1
rotates so that a linear velocity or an angular velocity is maintained constantly. A pickup
2
irradiates the surface of the disk
1
with laser light and reads the digital data recorded on the disk
1
in accordance with a variation of the reflected light. An analog signal processing circuit
3
processes an analog output signal from the pickup
2
and generates an Eight to Fourteen Modulation (EFM) signal indicating the digital data. The EFM signal is generated by EFM-modulating 8-bit data. As shown in
FIG. 2
, for EFM data, the first 24 bits of one frame are assigned to a synchronous field. A three bit connection field and a 14 bit data field are alternately assigned after the synchronous field.
A digital signal processing circuit
4
receives the EFM signal from the analog signal processing circuit
3
, applies EFM demodulation to the EMF signal and, as shown in
FIG. 2
, converts the 14-bit data to 8-bit data. In the EFM demodulation, 1-byte subcode data is fetched from the first data field after the synchronous signal and 32-bytes of symbol data are generated from the remaining data fields. The digital signal processing circuit
4
applies CIRC decoding to the 32-bytes of symbol data and generates 24-bytes of CD-ROM data.
The CD-ROM data is handled in units of sectors consisting of 2,352 bytes (24 bytes×98 frames), as shown in
FIG. 3. A
synchronous signal (12 bytes) and a header (four bytes) are assigned to the beginning of one sector. The synchronous signal is a fixed pattern indicating the top position of a sector. Information (minute/second/frame number: one byte each) about the absolute time that corresponds to an address on the disk and a mode identification code (one byte) that identifies a data format in the sector are assigned to the 4-byte header. User data, an error correction code (ECC) and an error detection code (EDC) are assigned to the 2,336 bytes following the header in accordance with the mode and the form.
For example, as shown in
FIG. 4
, in mode
1
, user data (2,048 bytes), an EDC (4 byes), zero (8 bytes) and an ECC (276 bytes) are defined. In form
1
of mode
2
, the subheader (8 bytes), user data (2,048 bytes), the EDC (4 bytes) and the ECC (276 bytes) are defined. In mode
2
form
2
, the subheader (8 bytes), user data (2,324 bytes) and the EDC (4 bytes) are defined.
A CD-ROM decoder
5
receives the CD-ROM data from the digital processing circuit
4
, performs a code error correction on the CD-ROM data and transfers the corrected CD-ROM data to a host computer in accordance with a request from the host computer. A buffer RAM
6
is connected to the CD-ROM decoder
5
and stores the CD-ROM data supplied from the digital signal processing circuit
4
to the CD-ROM decoder
5
for a predetermined time. Since the ECC and the EDC are set for the one sector CD-ROM data, at least one sector of CD-ROM data is stored in the buffer RAM
6
. Further, the several sectors of error-corrected CD-ROM data are stored in the buffer RAM
6
for the host computer.
A control microcomputer
7
controls the analog signal processing circuit
3
, the digital signal processing circuit
4
and the CD-ROM decoder
5
in accordance with a predetermined operation program. The control microcomputer
7
controls the analog signal processing circuit
3
, the digital signal processing circuit
4
and the CD-ROM decoder
5
in accordance with a request from the host computer to transfer the CD-ROM data to the host computer.
In the CD-ROM system
100
, header information is supplied to the control microcomputer
7
every sector. The control microcomputer
7
identifies the format of each sector of CD-ROM data based on the header information and controls the CD-ROM decoder
5
in accordance with the identified format.
When CD-ROM data is transferred to the host computer, it is necessary to identify the format of the sector being transferred. This is because the position of data in a sector differs depending on the mode, as shown in FIG.
4
. Thus, as previously discussed, the control microcomputer
7
identifies the format of each sector and transfers the user data to the host computer based on the identified format.
Further, in the CD-ROM data correction and detection process, it is necessary to identify the format of a sector to be processed. That is, if the ECC and the EDC are set in the CD-ROM data, the code error detection is performed after the code error correction. If only the EDC is set, only the code error detection is performed. The control microcomputer
7
switches the error processing based on the format of each sector.
In mode
1
, the format of each sector is determined by the mode identification code contained in the header of the CD-ROM data. In mode
2
, the format of each sector is determined from the subheader data. These determination operations increase the load on the control microcomputer
7
. In particular, if the operating speed of the host computer is increased, the load on the control microcomputer
7
increases, so that it is difficult for the control microcomputer
7
to adequately control the analog signal processing circuit
3
, the digital signal processing circuit
4
and the CD-ROM decoder
5
at high speed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a CD-ROM decoder having reduced load on the control microcomputer.
In one aspect of the present invention, a CD-ROM decoder that performs a code error correction and/or a code error detection on digital data partitioned in a plurality of sectors each having a predetermined format is provided. The digital data of each sector includes header information. The CD-ROM decoder includes a header information register that stores the header information contained in each sector of the digital data. A sector information conversion circuit is connected to the header information register to determine the format of each sector in accordance with the header information and generating sector information for each sector based on the determination result. The digital data of each sector and the sector information of each sector are stored in a buffer memory.
In another aspect of the present invention, a method for temporarily storing digital data partitioned in a plurality of sectors each having a predetermined format in a buffer memory is provided. First, a first address area for storing digital data of N (N is an integer of 2 or more) sectors are defined in the buffer memory. Then, a second address area for storing sector information for the N bytes are defined in the buffer memory. Each piece of sector information indicates the format of a corresponding sector of digital data. The digital data is stored in the first address area in units of sectors, and the sector information is stored in the second address area in correspondence with each sector of digital data.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 6226247 (2001-05-01), Sako et al.
patent: 6259659 (2001-07-01), Fechser et al.
patent: 6272084 (2001-08-01), Maeda
patent: 6285637 (2001-09-01), Manter et al.
patent: 6539518 (2003-03-
Ishibashi Masayuki
Suzuki Takayuki
Tsuda Hiroyuki
Baderman Scott
Damiano Anne L.
Fish & Richardson P.C.
Sanyo Electric Co,. Ltd.
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