Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-03-27
2004-02-24
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
06697915
ABSTRACT:
BACKGROUD OF THE INVENTION
The present invention relates to a CD-ROM decoder, and more particularly, to a CD-ROM decoder for correcting code errors included in digital data and transferring the corrected digital data to a computer.
FIG. 1
is a schematic block diagram of a prior art CD-ROM system
100
. The CD-ROM system
100
includes a pickup
2
, an analog signal processor
3
, a digital signal processor
4
, a CD-ROM decoder
5
, a buffer RAM
6
, and a microcomputer
7
.
A spiral record track is defined on a disc
1
. Digital data complying with a predetermined format is recorded along the record track. The digital data is generated through eight to fourteen modulation (EFM). The disc
1
is rotated at a constant linear velocity or a constant angular velocity.
The pickup
2
emits a laser beam against the disc
1
and generates from the reflected laser beam a voltage signal corresponding to the digital data recorded on the disc
1
.
The analog signal processor
3
shapes the waveform of the voltage signal in correspondence with the fluctuation of the voltage signal provided from the pickup
2
to generate an EFM signal.
The digital signal processor
4
performs EFM demodulation on the EFM signal provided from the analog signal processor
3
to covert the 14-bit digital data to 8-bit digital data and generates CD-ROM data. Further, the digital signal processor
4
uses a cross interleave Reed-Solomon code (CIRC) to detect and correct code errors. A frame is defined by 24 bytes of CD-ROM data. With reference to
FIG. 2
, a sector is defined by 2,352 (98 frames×24) bytes of CD-ROM data. A synchronization signal (12 bytes) and a header (4 bytes) are allocated to the head of each sector. The synchronization signal has a fixed pattern and indicates the head of each sector. Absolute time information (minutes/seconds/frame number: each 1 byte) and a mode identification code (1 byte) are included in the header. The absolute time information corresponds to an address on the disc
1
. The mode identification code is used to identify the format (mode) of the data in a sector. In accordance with the mode and form, user data, an error correction code (ECC), and an error detection code (EDC) are allocated to the 2,336 bytes following the header. For example, referring to
FIG. 3
, in mode 1, the user data (2,048 bytes), the EDC (4 bytes), ZERO (8 bytes), and the ECC (276 bytes) follow the header. In mode 2, formless, only the user data (2,336 bytes) follows the header. In form 1 of mode 2, a sub-header (8 bytes), user data (2,048 bytes), the EDC (4 bytes), and the ECC (276 bytes) follow the header. In form 2 of mode 2, the sub-header (8 bytes), the user data (2,334 bytes), and the EDC (4 bytes) follow the header.
The CD-ROM decoder
5
also corrects error codes included in the CD-ROM data provided from the digital signal processor
4
and transfers CD-ROM data (user data) to a host computer based on a request from the host computer.
The buffer RAM
6
is connected to the CD-ROM decoder
5
to store CD-ROM data in sector units for a predetermined time. The CD-ROM decoder
5
performs decoding to correct code errors in the CD-ROM data during the predetermined time.
The microcomputer
7
executes a predetermined control program so that the analog signal processor
3
, the digital signal processor
4
, and the CD-ROM decoder
5
are operated at predetermined timings. In response to a transfer request of the CD-ROM data from the host computer, the microcomputer
7
controls the analog signal processor
3
, the digital signal processor
4
, and the CD-ROM decoder
5
to transfer the requested data to the host computer.
Normally, the transfer of CD-ROM data is requested continuously. Thus, the CD-ROM data of the disc
1
is stored in the buffer RAM
6
prior to the transfer request (hereafter referred to as data pre-read). When the microcomputer
7
receives a data transfer request from a host computer, the microcomputer
7
first decides whether the transfer data has been stored in the buffer RAM
6
. If the transfer data has been stored in the buffer RAM
6
, the microcomputer
7
transfers the transfer data to the host computer from the CD-ROM decoder
5
. If the transfer data has not yet been stored in the buffer RAM
6
, the microcomputer
7
activates the pickup
2
to read the transfer data.
Accordingly, in the CD-ROM system
100
, the decision of whether the transfer data has been stored (the checking of pre-read data) when the host computer request the transfer of CD-ROM data is performed by the microcomputer
7
. Further, the processes described above, including the checking of the pre-read data are properly performed in accordance with a control program. However, an increase in the operating speed of the CD-ROM system
100
increases the load on the microcomputer
7
. As a result, the microcomputer
7
may not be able to follow the operations of the analog signal processor
3
, the digital signal processor
4
, and the CD-ROM decoder
5
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a CD-ROM decoder that decreases the load on the microcomputer, while appropriately performing data transfer control.
To achieve the above object, the present invention provides a CD-ROM decoder for temporarily storing in a buffer memory in sector units digital data having a predetermined number of bytes and a predetermined format, processing the digital data by correcting and detecting code errors included in the digital data, and transferring the processed digital data. The CD-ROM decoder includes a check head register for storing a first address of the buffer memory when the storing of the processed digital data to the buffer memory is started. A check sector counter counts the number of sectors of the processed digital data stored in the buffer memory to generate a count value. A command decision circuit connected to the check head register and the check sector for deciding whether the digital data requested to be transferred is stored in the buffer memory based on the first address, the count value, and a head address of the digital data requested to be transferred. The command decision circuit permits the CD-ROM decoder to transfer the processed digital data when deciding that the digital data requested to be transferred is stored in the buffer memory.
The present invention further provides a method for transferring in sector units digital data having a predetermined number of bytes and a predetermined format with a CD-ROM decoder. The CD-ROM decoder includes a command decision circuit for deciding whether data requested to be transferred is stored in a buffer memory. The method includes temporarily storing the digital data in the buffer memory, processing the digital data by correcting and detecting code errors included in the digital data to generate processed digital data, storing a first address of the buffer memory when the storing of the processed digital data to the buffer memory is started, and counting the number of sectors of the processed digital data stored in the buffer memory to generate a count value. The count value corresponds to an address interval of the processed digital data occupying the buffer memory. The method further includes deciding whether the digital data requested to be transferred is stored in the buffer memory with the command decision circuit by comparing a comparison address decided from the first address and the address interval to a head address of the digital data requested to be transferred, and permitting the CD-ROM decoder to transfer the processed digital data with the command decision circuit when the digital data requested to be transferred is decided to be stored in the buffer memory.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
REFERENCES:
patent: 5220551 (1993-06-01), Tateishi et al.
patent: 5553261 (1996-09-01), Hasbun et al.
patent: 60
Ishibashi Masayuki
Suzuki Takayuki
Tsuda Hiroyuki
Choi Woo H.
Kim Matthew
Sheridan Ross PC
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