CCD array memory device having dual, independent clocks of diffe

Details CCD array memory device having dual, independent clocks of diffe CCD array memory device having dual, independent clocks of diffe

1993-06-16

1994-12-13

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Semiconductive

365 77, 365 78, 365219, 365240, G11C 1134

Patent

active

053734645

ABSTRACT:
The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption.
A memory device according to this invention downsizes a block of a memory cell by circulating data on a plural number of linear CCD arrays which are for storing data by an electric charge on a cell and keeping analog data, which sets a clock generation means for circulating data on all arrays and another clock generation means for circulating at a high speed only the array loops having necessary data.

REFERENCES:
patent: 4165539 (1979-08-01), Aichelmann, Jr.
patent: 4322635 (1982-03-01), Redwine
patent: 4388701 (1983-06-01), Aichelmann, Jr. et al.
patent: 4725748 (1988-02-01), Hayes et al.
Electrical Engineering Handbook, Editor-in-Chief, Richard C. Dorf, pp. 1726-1727 and 1735, CRC Press 1993.

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