Cavity grid array integrated circuit package

Details Cavity grid array integrated circuit package Cavity grid array integrated circuit package

1998-03-18

1999-10-05

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

257774, 257698, 257692, 174263, H01L 2348, H01L 2352, H01L 2940

Patent

active

059629223

ABSTRACT:
A flat package for integrated circuit chip has a substrate with plated through holes. The top flange of a plated through hole is interconnected to a terminal of the IC chip. The bottom flange of the through hole has a cavity recessed into the substrates. A solder is placed between a circuit contact on a mother board and the bottom flange. Upon heating, the solder rises to fill the cavity, to make connection between the terminal on the IC chip and the contact on the mother board.

REFERENCES:
patent: 4664962 (1987-05-01), DesMarais, Jr.
patent: 5315072 (1994-05-01), Arai et al.
patent: 5404044 (1995-04-01), Booth et al.
patent: 5406034 (1995-04-01), Frei et al.
patent: 5541368 (1996-07-01), Swamy
patent: 5689091 (1997-11-01), Hamzehdoost et al.
patent: 5783865 (1998-07-01), Higashiguchi et al.

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