Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
1998-11-30
2001-06-26
Valentine, Donald R. (Department: 1741)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S279000, C204S297010
Reexamination Certificate
active
06251236
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to deposition of a metal layer onto a substrate. More particularly, the present invention relates to an apparatus used in electroplating a metal layer onto a substrate.
2. Background of the Related Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to less than 250 nanometers, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many traditional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), have difficulty filling structures where the aspect ratio exceed 4:1, and particularly where it exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized features having high aspect ratios wherein the ratio of feature height to feature width can be 4:1 or higher. Additionally, as the feature widths decrease, the device current remains constant or increases, which results in an increased current density in the feature.
Elemental aluminum (Al) and its alloys have been the traditional metals used to form lines and plugs in semiconductor processing because of aluminum's perceived low electrical resistivity, its superior adhesion to silicon dioxide (SiO
2
), its ease of patterning, and the ability to obtain it in a highly pure form. However, aluminum has a higher electrical resistivity than other more conductive metals such as copper, and aluminum also can suffer from electromigration leading to the formation of voids in the conductor.
Copper and its alloys have lower resistivities than aluminum and significantly higher electromigration resistance as compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increase device speed. Copper also has good thermal conductivity and is available in a highly pure state. Therefore, copper is becoming a choice metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features, such as a 4:1, having 0.35&mgr; (or less) wide vias are limited. Precursors for CVD deposition of copper are ill-developed, and physical vapor deposition into such features produces unsatisfactory results because of voids formed in the features.
As a result of these process limitations, plating which had previously been limited to the fabrication of lines on circuit boards, is just now being used to fill vias and contacts on semiconductor devices. Metal electroplating is generally known and can be achieved by a variety of techniques. A typical method generally comprises physical vapor depositing a barrier layer over the feature surfaces, physical vapor depositing a conductive metal seed layer, preferably copper, over the barrier layer, and then electroplating a conductive metal over the seed layer to fill the structure/feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Plating is achieved by delivering power to the seed layer and then exposing the substrate plating surface to an electrolytic solution containing the metal to be deposited, such as copper. The seed layer provides good adhesion for the subsequently deposited metal layers, as well as a conformal layer for even growth of the metal layers thereover. However, a number of obstacles impairs consistently reliable electroplating of copper onto substrates having nanometer-sized, high aspect ratio features. Generally, these obstacles include providing uniform power distribution and current density across the substrate plating surface to form a metal layer having uniform thickness.
One current method for providing power to the plating surface uses contact pins which contact the substrate seed layer. Present designs of cells for electroplating a metal on a substrate are based on a fountain plater configuration.
FIG. 1
is a cross sectional view of a simplified fountain plater
10
incorporating contact pins. Generally, the fountain plater
10
includes an electrolyte container
12
having a top opening, a substrate holder
14
disposed above the electrolyte container
12
, an anode
16
disposed at a bottom portion of the electrolyte container
12
and a contact ring
20
contacting the substrate
48
. The contact ring
20
, shown in detail in
FIG. 2
, comprises a plurality of contact pins
56
distributed about the peripheral portion of the substrate
48
to provide a bias thereto. Typically, the contact pins
56
consist of a conductive material such as tantalum (Ta), titanium (Ti), platinum (Pt), gold (Au), copper (Cu), or silver (Ag). The plurality of contact pins
56
extend radially inwardly over the edge of the substrate
48
and contact a conductive seed layer of the substrate
48
at the tips of the contact pins
56
. The pins
56
contact the seed layer at the extreme edge of the substrate
48
to minimize the effect of the pins
56
on the devices to be ultimately formed on the substrate
48
. The substrate
48
is positioned above the cylindrical electrolyte container
12
, and electrolyte flow impinges perpendicularly on the substrate plating surface during operation of the cell
10
.
The contact ring
20
, shown in
FIG. 2
, provides electrical current to the substrate plating surface
54
to enable the electroplating process. Typically, the contact ring
20
comprises a metallic or semi-metallic conductor. Because the contact ring is exposed to the electrolyte, conductive portions of the contact ring
20
, such as the pins
56
, accumulate plating deposits. Deposits on the contact ring
20
, and particularly the pins
56
, changes the physical and chemical characteristics of the conductor and eventually deteriorates the contact performance, resulting in plating defects due to non-uniform current distribution on the surface be plated. Efforts to minimize unwanted plating include covering the contact ring
20
and the outer surface of pins
56
with a non-plating or insulation coating.
However, while insulation coating materials may prevent plating on the outer pin surface, the upper contact surface remains exposed. Thus, after extended use of the fountain plater, solid deposits are inevitably formed on the pins. Because the deposits each have unique geometric profiles and densities, they produce varying contact resistance from pin to pin at the interface of the contact pins and seed layer resulting in a non-uniform distribution of current densities across the substrate. Also, the contact resistance at the pin/seed layer interface may vary from substrate to substrate, resulting in inconsistent plating distribution between different substrates using the same equipment. Furthermore, the plating rate tends to be increased near the region of the contact pins and is dissipated at further distances therefrom. A fringing effect of the electrical field also occurs at the edge of the substrate due to the localized electrical field emitted by the contact pins, causing a higher deposition rate near the edge of the substrate where the pin contac
Applied Materials Inc.
Thomason Moser & Patterson LLP
Valentine Donald R.
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