Catalytic nucleation monolayer for metal seed layers

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S221000, C438S240000, C438S597000, C257S304000, C257S310000, C257S374000

Reexamination Certificate

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11269402

ABSTRACT:
A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.

REFERENCES:
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patent: 2002/0009884 (2002-01-01), Pyo
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patent: 2004/0248403 (2004-12-01), Moon et al.
patent: 2005/0124154 (2005-06-01), Park et al.
Pending U.S. Appl. No. 11/233,297, filed Sep. 21, 2005; Inventor: Arnel Fajardo et al.

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