Catalyst patterning for nanowire devices

Details Catalyst patterning for nanowire devices Catalyst patterning for nanowire devices

2002-04-05

2004-12-14

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S486000

Reexamination Certificate

active

06831017

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to nanowires and more particularly, to ways in which to pattern catalyst sites from which nanowires are grown.
Nanowires are of interest for forming chemical or biological sensors, field emitters for flat panel displays, and other devices. Nanowires such as carbon nanotubes may be metallic in nature. Single-crystal semiconductor nanowires may also be grown. A typical nanowire may have a diameter on the order of 10-100 nm and a length of 0.5-5 &mgr;m. Applications and potential applications for devices based on nanowire structures include sensors and field emitters for flat panel displays.
The growth of nanowires such as single and multiple wall carbon nanotubes and semiconductor nanowires has been demonstrated experimentally. Nanowire growth may be initiated using catalysts deposited on the surface of a substrate. Improved techniques for patterning such catalysts are needed.
It is therefore an object of the present invention to provide improved ways in which to pattern nanowire catalysts for nanowire devices.
SUMMARY OF THE INVENTION
Nanowire catalyst patterning methods and nanowire structures fabricated using patterned catalyst layers are provided. Nanowires may be formed on substrates such as silicon, quartz, glass, or other suitable substrate materials. An optional electrode layer may be formed on the substrate. The electrode layer may, for example, be formed of titanium, gold, or platinum or other metals or conductive materials. The electrode layer may be patterned. For example, photolithographic techniques may be used to pattern the electrode layer into an array of pads.
A catalyst layer may be used to seed the growth of nanowires on the pads or other portions of substrate surface. Catalyst sites may be distributed in a random pattern or may be purposefully distributed in a known pattern. A known pattern of “dots” of catalyst may, for example, be used to form a regular array of nanowires with a desired spacing between nanowires and desired wire diameters.
Catalyst sites may be patterned using a number of suitable techniques. For example, e-beam lithography, a metal deposition technique such as evaporation, and the lift-off process may be used to form catalyst sites. Other suitable catalyst site formation techniques that may be used include techniques based on heating deposited metal so that it collects into discrete metal areas or clumps (“metal migration”), heat-collapsible porous polymer spheres filed with metal salts, techniques in which metal is evaporated through a thin-film assembly of microscopic spheres (e.g., spheres 100 nm to 100 &mgr;m in diameter) that have been temporarily placed on the substrate surface, lithographic techniques (e.g., ultraviolet (UV) lithography such as deep UV (DUV) lithography or extreme UV (EUV) lithography, etc.), X-ray or ion beam lithography, electrochemical deposition, electroless deposition, or soft lithography (e.g., when a damp “stamp” is used to impress a pattern of catalytic “ink” on a substrate), etc.
Nanowires may be grown on the catalyst sites by known growth techniques such as thermal or plasma chemical vapor deposition techniques or other suitable nanowire growth techniques.
If desired, additional processing may be performed after the nanowires have been grown. For example, an insulating layer may be grown on the nanowires to insulate the nanowires from each other and to provide mechanical stability. The insulating layer may be planarized using chemical-mechanical polishing. The substrate on which the nanowires have been grown may be diced into individual die, each of which contains a portion of the nanowire structures formed on the substrate. The die may be packaged in suitable packages and may be interconnected with circuitry and other devices.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.


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