Castellated chip-scale packages and methods for fabricating...

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Substrate dicing

Reexamination Certificate

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C438S068000, C438S113000, C438S460000, C438S464000, C438S459000

Reexamination Certificate

active

10717421

ABSTRACT:
A method for fabricating a chip-scale package includes securing a device substrate that carries at least two adjacent semiconductor devices to a sacrificial substrate. The sacrificial substrate may include conductive elements on a surface thereof, which are located so as to align along a street between each adjacent pair of semiconductor devices on the device substrate. The device substrate is then severed along each street and the newly formed peripheral edge of each semiconductor device coated with dielectric material. If the sacrificial substrate includes conductive elements, they may be exposed between adjacent semiconductor devices and subsequently serve as lower sections of contacts. Peripheral sections of contacts are formed on the peripheral edge. Upper sections of the contacts may also be formed over the active surfaces of the semiconductor devices. Once the contacts are formed, the sacrificial substrate is substantially removed from the back sides of the semiconductor devices.

REFERENCES:
patent: 4956694 (1990-09-01), Eide
patent: 5111278 (1992-05-01), Eichelberger
patent: 5138115 (1992-08-01), Lam
patent: 5266833 (1993-11-01), Capps
patent: 5313096 (1994-05-01), Eide
patent: 5434745 (1995-07-01), Shokrgozar et al.
patent: 5440452 (1995-08-01), Kitahara
patent: 5502667 (1996-03-01), Bertin et al.
patent: 5541450 (1996-07-01), Jones et al.
patent: 5639695 (1997-06-01), Jones et al.
patent: 5723901 (1998-03-01), Katsumata
patent: 5752182 (1998-05-01), Nakatsuka et al.
patent: 5834162 (1998-11-01), Malba
patent: 5925924 (1999-07-01), Cronin et al.
patent: 5950070 (1999-09-01), Razon et al.
patent: 5986209 (1999-11-01), Tandy
patent: 6004867 (1999-12-01), Kim et al.
patent: 6034438 (2000-03-01), Petersen
patent: 6072236 (2000-06-01), Akram et al.
patent: 6228684 (2001-05-01), Maruyama
patent: 6252300 (2001-06-01), Hsuan et al.
patent: 6306680 (2001-10-01), Fillion et al.
patent: 6316287 (2001-11-01), Zandman et al.
patent: 6323546 (2001-11-01), Hsuan et al.
patent: 6326689 (2001-12-01), Thomas
patent: 6335225 (2002-01-01), Doan
patent: 6344401 (2002-02-01), Lam
patent: 6352923 (2002-03-01), Hsuan et al.
patent: 6358833 (2002-03-01), Akram et al.
patent: 6376769 (2002-04-01), Chung
patent: 6379982 (2002-04-01), Ahn et al.
patent: 6379999 (2002-04-01), Tanabe
patent: 6461956 (2002-10-01), Hsuan et al.
patent: 6504244 (2003-01-01), Ichinose et al.
patent: 6521485 (2003-02-01), Su et al.
patent: 6521995 (2003-02-01), Akram et al.
patent: 6552426 (2003-04-01), Ishio et al.
patent: 6562647 (2003-05-01), Zandman et al.
patent: 6576992 (2003-06-01), Cady et al.
patent: 6582992 (2003-06-01), Poo et al.
patent: 6603191 (2003-08-01), Wakabayashi et al.
patent: 6611052 (2003-08-01), Poo et al.
patent: 6656827 (2003-12-01), Tsao et al.
patent: 6693358 (2004-02-01), Yamada et al.
patent: 6710454 (2004-03-01), Boon
patent: 6818977 (2004-11-01), Poo et al.
patent: 6841418 (2005-01-01), Jeung et al.
patent: 6849802 (2005-02-01), Song et al.
patent: 6855572 (2005-02-01), Jeung et al.
patent: 6856023 (2005-02-01), Muta et al.
patent: 6876061 (2005-04-01), Zandman et al.
patent: 7074696 (2006-07-01), Frankowsky et al.
patent: 2001/0009300 (2001-07-01), Sugimura
patent: 2001/0042901 (2001-11-01), Maruyama
patent: 2002/0017398 (2002-02-01), Hackie et al.
patent: 2002/0038890 (2002-04-01), Ohuchi
patent: 2002/0048906 (2002-04-01), Sakai et al.
patent: 2002/0079567 (2002-06-01), Lo et al.
patent: 2002/0158326 (2002-10-01), Furuya et al.
patent: 2002/0197770 (2002-12-01), Irie
patent: 2003/0080398 (2003-05-01), Badehi
patent: 2003/0102160 (2003-06-01), Gaudiello et al.
patent: 2003/0134453 (2003-07-01), Prabhu et al.
patent: 2003/0162326 (2003-08-01), Tsubosaki et al.
patent: 2003/0209772 (2003-11-01), Prabhu
patent: 2004/0140573 (2004-07-01), Pu et al.
patent: 2004/0156177 (2004-08-01), Higashitani
patent: 2004/0251525 (2004-12-01), Ziber et al.
patent: 59-27549 (1984-02-01), None
patent: 59-43556 (1984-03-01), None
patent: 363232342 (1988-09-01), None
patent: 5-75014 (1993-03-01), None
patent: 6-97225 (1994-04-01), None
patent: 2001-44361 (2001-02-01), None
patent: 02001210521 (2001-08-01), None
patent: 02003008066 (2003-01-01), None
NN81055595: Edge Mounted MLC Packaging Scheme. May 1981; IBM Technical Disclosure Bulletin, May 1981 US: vol. 23, Issue #12, p. #5595-5598; Publication Date: May 1, 1981.
Australian Search Report, Apr. 15, 2005, 5 pages.
U.S. Appl. No. 10/183,820, filed Jun. 27, 2002.
U.S. Appl. No. 10/197,986, filed Jul. 17, 2002.
U.S. Appl. No. 10/440,590, filed May 19, 2003.

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