Cascode SSTL output buffer using source followers

Details Cascode SSTL output buffer using source followers Cascode SSTL output buffer using source followers

2002-09-26

2004-08-10

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C326S031000, C327S108000, C327S530000, C327S534000

Reexamination Certificate

active

06774665

ABSTRACT:

BACKGROUND OF THE INVENTION
As shown in
FIG. 1
, a typical computer system
10
includes at least a microprocessor
12
(often referred to and known as “CPU”) and some form of memory
14
. The microprocessor
12
has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system
10
. Specifically,
FIG. 1
shows the computer system
10
having the microprocessor
12
, memory
14
, crystal
18
, integrated circuits (ICs)
16
that have various functionalities, and communication paths
19
, i.e., buses and wires, that are necessary for the transfer of data among the aforementioned components of the computer system
10
.
In order to keep pace with improving technologies, computer system and circuit designers are constantly trying to improve their designs through the most cost-effective means. As faster versions of a particular CPU become available, a designer will often try to improve the throughput of their existing design by simply increasing the CPU clock frequency. However, after a certain point, the speed of the system's main memory becomes a limiting factor in optimizing the throughput of the system. To this end, designers have produced faster memories, which, in turn, has necessitated high-speed memory interfaces.
One type of design that has been used for high-speed memory interface applications involves the use of stub series termination logic (SSTL). A SSTL interface standard was created by the Joint Electron Device Engineering Council (JEDEC) to provide a termination scheme for high speed signaling in applications such as double data rate synchronous dynamic random access memory (DDR-SDRAM). The SSTL interface standard specifies particular switching characteristics such that high operating frequencies are available. As operating frequencies continue to increase and as the demand for faster memory interfaces has and continues to grow, the SSTL interface standard continues to enjoy wide acceptance.
The SSTL interface standard defines operation around a reference voltage potential. A high or low bit may be transmitted as a voltage potential that is higher or lower than a reference voltage potential, respectively. There is a likelihood that the supply voltage for the SSTL interface will exceed the voltage tolerances of low-voltage transistors that are designed to operate at voltages below that of the SSTL interface. If a large voltage is placed across one of these low-voltage transistors, the gate oxide layer of the transistor may breakdown, which, in turn, could cause circuit malfunction
FIG. 2
shows a typical SSTL output buffer pull down circuit
200
that includes resistors R
1
202
and R
2
204
to provide a bias signal on node N
1
211
. A cascode circuit includes transistors
218
and
216
. The cascode circuit is used to prevent the possible breakdown of transistors
218
and
216
when an output signal
215
is at a maximum voltage potential.
The output signal
215
is pulled down depending on an input_low signal. The input_low signal may have a voltage potential range less than a maximum voltage potential of the output signal
215
, where the voltage potential range is defined as the difference between a maximum and minimum voltage potential applied on the input_low signal.
In
FIG. 2
, the transistor
218
is connected to the bias signal on node N
1
211
. To reduce power consumption, resistors R
1
202
and R
2
204
are typically large valued to reduce current through the voltage divider formed by resistors R
1
202
and R
2
204
. During operation of the SSTL output buffer, the SSTL output buffer pull down circuit
200
may be designed to have a voltage potential on the input_low signal that is less than V
DD
and turns on the transistor
216
. Accordingly, the SSTL output buffer pull down circuit
200
pulls down the voltage potential of the output signal
215
. Inherent capacitances
230
and
233
formed between the output signal
215
and the node N
1
211
, and the signal
217
and the node N
1
211
, respectively, may cause the voltage potential of the bias signal on node N
1
211
to decrease. Because the resistors R
1
202
and R
2
204
are typically large valued, the resistors R
1
202
and R
2
204
may be slow to restore the desired bias voltage potential of the bias signal on node N
1
211
. Accordingly, the resistance formed by transistor
218
increases, and the output signal
215
may not be pulled down at the desired transition rate or obtain the desired voltage potential. Conversely, resistors R
1
202
and R
2
204
may be moderate or small valued to improve the ability to maintain a desired bias voltage potential of the bias signal on node N
1
211
. As the combined value of resistors R
1
202
and R
2
204
decrease, the power and current consumed by the resistors R
1
202
and R
2
204
increases.
FIG. 3
shows a typical SSTL output buffer pull up circuit
300
that includes resistors R
1
302
and R
2
304
to provide a bias signal on node N
1
311
. A cascode circuit includes transistors
316
and
318
. The cascode circuit is used to prevent the possible breakdown of transistors
316
and
318
when an output signal
315
is at a minimum voltage potential.
The output signal
315
is pulled up depending on an input_high signal. The input_high signal may have a voltage potential range less than a maximum voltage potential of the output signal
315
, where the voltage potential range is defined as the difference between a maximum and minimum voltage potential applied on the input_high signal.
In
FIG. 3
, the transistor
318
is connected to the bias signal on node N
1
311
. To reduce power consumption, resistors R
1
302
and R
2
304
are typically large valued to reduce current through the voltage divider formed by resistors R
1
302
and R
2
304
. During operation of the SSTL output buffer, the SSTL output buffer pull up circuit
300
may be designed to have a voltage potential range on the input_high signal that is less than the V
DD
to V
SS
range and turns on the transistor
316
. Accordingly, the SSTL output buffer pull up circuit
300
pulls up the voltage potential of the output signal
315
. Inherent capacitances
330
and
333
formed between the output signal
315
and the node N
1
311
, and the signal
317
and the node N
1
311
, respectively, may cause the voltage potential of the bias signal on node N
1
311
to increase. Because the resistors R
1
302
and R
2
304
are typically large valued, the resistors R
1
302
and R
2
304
may be slow to restore the desired bias voltage potential of the bias signal on node N
1
311
. Accordingly, the resistance formed by transistor
318
increases, and the output signal
315
may not be pulled up at the desired transition rate or obtain the desired voltage potential. Conversely, resistors R
1
302
and R
2
304
may be moderate or small valued to improve the ability to maintain a desired bias voltage potential of the bias signal on node N
1
311
. As the combined value of resistors R
1
302
and R
2
304
decrease, the power and current consumed by the resistors R
1
302
and R
2
304
increases.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, an integrated circuit comprises a biasing circuit arranged to generate a first bias signal; a source follower circuit operatively connected to the first bias signal where the source follower circuit is arranged to generate a second bias signal dependent on the first bias signal; and a cascode circuit operatively connected to the second bias signal where the cascode circuit is arranged to generate an output signal dependent on the second bias signal and an input signal.
According to another aspect, a method for performing a stub series termination logic operation comprises generating a first bias signal dependent on a power supply voltage potential; generating a second bias signal dependent on the first bias signal; and generating an output signal dependent on the second bias signal and an input signal

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