Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-29
2004-10-26
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S360000, C327S375000
Reexamination Certificate
active
06809386
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits (IC's) and, more particularly to circuitry within the IC to drive the input/output signal.
BACKGROUND OF THE INVENTION
An IC chip electrically communicates with off-chip electronics to exchange information. The IC chip may employ a different voltages than are employed by off-chip electronics. Accordingly, the interface between the IC chip and off-chip electronics must accommodate the voltage differences. One such interface includes a mixed voltage input/output (“I/O”) driver as discussed in ESD Protection For Mixed-Voltage I/O Using NMOS Transistors Stacked In A Cascode Configuration, by Warren Anderson and Davis Krakauer and published in EOS/ESD Symposium 98-55, herein incorporated by reference.
FIGS. 2 and 3
of this publication show an ESD protection structure including two NMOS transistors in a cascode configuration, where the transistors are merged into the same active area of a substrate. The two NMOS transistors allows a 5V signal to be dropped to 3.3V during normal operation while providing a parasitic lateral NPN bipolar transistor during electrostatic discharge. Under ESD conditions, the stacked transistors operate in snapback with the bipolar effect occurring between the source of the bottom NMOS transistor and drain of the top NMOS transistor. While this I/O driver has been used for some generic designs, it has been a continuing challenge to balance electrostatic discharge protection performance and I/O performance. Accordingly, it is desired to improve upon the performance of a cascode MOS driver. More specifically, there is a need to remove the ESD design constraints from drivers to achieve maximum I/O performance.
SUMMARY OF THE INVENTION
Upon reading and understanding the present disclosure it is recognized that the inventive subject matter described herein provides novel structures and methods and may include novel structures and methods not expressed in this summary. The following summary is provided to give the reader a brief summary which is not intended to be exhaustive or limiting and the scope of the invention is provided by the attached claims and the equivalents thereof.
An embodiment of the present invention includes an I/O device having two transistors in a cascode configuration with a shared diffusion region with a spacing region therein. In an embodiment, the spacing region is non-conductive. In an embodiment, the transistors are NMOS transistors.
An embodiment of the present invention includes integrated circuit that includes a substrate, a first MOS transistor, and a second MOS transistor in a cascode configuration with the first MOS transistor. The first MOS transistor and the second MOS transistor have a shared diffusion region that has a barrier region therein. The barrier region divides the shared diffusion region into two sub-regions. The sub-regions being spaced from each other by the barrier region. One subregion is the source of the first transistor. The second sub-region is the drain of the second transistor.
An embodiment of the present invention includes an integrated circuit having a substrate including an active well, a first MOS transistor connected to the active well, and a second MOS transistor connected to the active well, the second transistor being in a cascode configuration with the first transistor with the source of the first transistor and the drain of the second transistor being connected to a shared region. The cascode connected transistors form a parasitic bipolar transistor in the active well between the drain of the first transistor and the source of the second transistor. The shared region includes a spacing separating the source of the first transistor and the drain of the second transistor.
An embodiment of the present invention includes an integrated circuit including a substrate, a contact pad on the substrate, and an I/O driver circuit on the substrate and connected to the contact pad. The I/O driver circuit includes a first MOS transistor on the substrate and a second MOS transistor in a cascode configuration with the first MOS transistor. The first MOS transistor and the second MOS transistor having a shared diffusion region, the shared diffusion region having a spacing region therein.
An embodiment of the present invention includes a cascode I/O driver that has one MOS transistor having a grounded gate and another MOS transistor having a floating gate.
An embodiment of the present invention includes a method of forming an I/O driver device including forming a first transistor in a substrate, forming a second transistor in the substrate having a shared region with the first transistor, and forming a barrier in the shared region. In an embodiment, the first transistor and the second transistor are simultaneously formed in the substrate such that the first and second transistors are in a cascode configuration with a shared region.
An embodiment of the present invention includes improving I/O driver operation of a cascode-type driver of an integrated circuit by inserting a gap in the common node of the cascode-connected transistors. This is achieved by removing ESD design constraints from the design of the I/O driver.
Other embodiments of the present invention include electrical I/O systems that include and I/O driver and an electrostatic discharge circuit and methods for forming the systems.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
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Anderson, Warren R., et al., “ESD Protection for Mixed-Voltage I/O Using NMOS Transistors Stacked in a Cascode Configuration”,20th Annual International EOS/ESD Symposium, IEEE Catalog No. 98TH8347, (1998), pp. 98-54 thru 98-62, ESD Association, Rome, New York.
Chaine Michael D.
Ma Manny K. F.
Schwegman Lundberg Woessner & Kluth P.A.
Wilson Scott R.
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