Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-08-05
2003-10-21
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S371000, C375S373000, C375S374000, C375S375000, C375S377000, C375S354000, C375S282000, C375S241000, C375S242000, C331S00100A, C331S017000, C327S149000, C327S150000, C341S061000, C341S143000, C341S144000, C341S146000, C341S126000, C341S128000, C341S129000
Reexamination Certificate
active
06636575
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to digital information systems. More particularly, the present invention relates to a method and system for rapidly synchronizing two or more digital communications systems.
BACKGROUND ART
The transmission of digital information and data between systems has become an essential part of commonly used systems. With such systems, information content is transmitted and received in digital form as opposed to analog form. Information long associated with analog transmission techniques, for example, television, telephone, music, and other forms of audio and video, are now being transmitted and received in digital form. The digital form of the information allows signal processing techniques not practical with analog signals. In most applications, the user has no perception of the digital nature of the information being received.
Traditional modes of communication often occur in “real time.” For example, a telephone conversation occurs in real time. A “live” television sports broadcast occurs in real time. Users have come to expect these and other such traditional forms of communication to be in real time. Thus, digital transmission and reception techniques and systems need to provide for the real time transmission and reception of information.
There is a problem, however, in that digital communication between devices distant from each other usually precludes the availability of identical sampling frequencies. Except for those cases where a distinct clocking hierarchy structure can be defined and a common distributed clock source employed, there will be some difference between the sample rate of one device (e.g., the transmitter) and the sample rate of the other device (e.g., the receiver).
Prior Art
FIG. 1
shows a typical prior art digital information transmission and reception system
100
. In system
100
, a signal source
101
, for example, a video camera, generates an analog input signal. The input signal is coupled to a sampler-ADC (analog to digital converter)
102
, where it is sampled and encoded into a digital pulse code modulated signal. This signal is transmitted across a transmission link to a sampler
103
. Sampler
103
is coupled to a DAC (digital to analog converter) reconstruction filter
104
. The sampler
103
samples the pulse code modulated signal received via the transmission link. The sampling creates a digital signal, which is subsequently coupled to the DAC-reconstruction filter where it is decoded and filtered into an output signal. The output signal represents the input signal from signal source
101
.
To maintain synchronization between the devices on either side of the communications link, sophisticated synchronization technology has been developed. In most instances, the synchronization technology functions adequately. Consequently, digital communications systems (e.g., digital television, digital telephony, etc.) have proliferated and become widely accepted. The synchronization performance obtainable with conventional, prior art synchronization technology is sufficient to allow most applications (e.g., digital television) to function as intended.
Prior Art
FIG. 2
shows a digital communications system
200
employing a typical prior art synchronization scheme. System
200
includes a transmitting device
201
sending a data signal to a receiving device
202
. Transmitting device
201
provides a transmitter clock signal to a phase comparison circuit, phase locked loop (PLL)
203
. PLL
203
generates a voltage output, V
out
, which is coupled to a VCO (voltage controlled oscillator)
205
. V
out
controls the frequency of a clock signal, CLOCK A, generated by VCO
205
. CLOCK A is coupled to a frequency divider
204
, where it is divided, typically by some large integer factor, to produce a clock signal CLOCK B. PLL
203
compares the phase of CLOCK B and the transmitter clock and adjusts V
out
until CLOCK B and the transmitter clock are in phase.
When the transmitter clock and CLOCK B are in phase, PLL
203
supplies a lock indication signal to receiving device
202
, informing the device it can now reliably use CLOCK B to sample the DATA signal from transmitting device
201
. Only after this time (e.g., phase lock) can reliable communication occur.
It should be noted that the receiving device
202
, as with most digital communications systems, is able to adjust its clock frequencies within a certain range “F
w
” about a nominal frequency “F
o
”, at a certain rate. When communication is initiated between the transmitter device
201
and the receiving device
202
, the initial phase difference between the transmitter clock and the receiver clock can be any value within a range of zero degrees to 180 degrees. Hence, based upon the rate at which the frequency and phase can be adjusted, and based upon the size of the range, system
200
will require a significant amount of time to acquire phase lock.
For example, in case where system
200
is a DECT (Digital Enhanced Cordless Telephony) system connected to an ISDN central office branch where the transmitter clock frequency=8 kHz and (F
w
/F
o
,)=10
−5
, phase lock time may run up to seven seconds. Phase lock time can increase even more significantly if the transmitter clock frequency or the receiver clock frequency (e.g., CLOCK B) deviates from F
o
. Acquiring phase lock requires that the CLOCK B signal be tuned to deviate as much as possible from the transmitter clock frequency so that the phases of both frequencies approach each other as fast as possible, with CLOCK B being slowly adjusted by PLL
203
and VCO
205
. This resembles two trucks on an uphill highway trying to catch up with each other, having the same engine horsepower.
Referring still to system
200
of
FIG. 2
, frequency synchronization between the transmitting device
201
and the receiving device
202
is achieved by synchronizing the phase of both devices with the phase of PLL
203
. This method is well known and widely used in the art, and results in achieving synchronicity both in frequency and phase between the transmitting device
201
and receiving device
202
.
Given the fact that two communication devices, transmitting device
201
and receiving device
202
, can adjust their respective clock rates within a certain narrow window, and there is an initial phase difference between their clock signals, one can calculate the minimum time required for the worst case synchronization (for example, where the transmitter clock signal and the receiver device clock signal CLOCK B are initially 180° out of phase). For a DECT system, where F
o
is 8 kHz and F
w
is approximately 10
−5
(=10 ppm), phase lock time may run up to 6.5 seconds. Lock time can increase significantly if the transmitter clock signal or the receiver device clock signal deviate from F
o
. Worst-case lock time (still assuming the transmitter clock and receiver clock are at F
o
) can be calculated from the cycle duration of the transmitter clock or the receiver clock, the startup phase difference P
do
=62.5 &mgr;s, and the maximum possible cycle duration difference 10
−5
/F
A
=1.25 ns between F
A
and F
B
(where F
A
and F
B
, are the transmitter clock and receiver clock, respectively). Acquiring phase lock requires that one of the two frequencies (F
A
or F
B
) be tuned to deviate as much as possible from the other so that the phases of both frequencies approach each other as fast as possible. The initial phase difference of P
do
=62.5 &mgr;s is thereby decreased in steps of approximately 1.25 ns per cycle of F
A
, taking −50,000 cycles of F
A
, equivalent to −6.25 seconds plus the implementation loss of the phase-lock-loop circuit PLL.
Synchronization has to be achieved each time the phone rings before useful communication can start. In system
200
, phase lock has to be achieved each time the phone rings before useful communication can start. Prior to synchronization, no reliable communication can be established between the two digital tele
Chin Stephen
Koninklijke Philips Electronics , N.V.
Munoz Guillermo
Zawilski Peter
LandOfFree
Cascading PLL units for achieving rapid synchronization... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cascading PLL units for achieving rapid synchronization..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cascading PLL units for achieving rapid synchronization... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3158613