Cascading FIFO memory devices for sequential storing

Details Cascading FIFO memory devices for sequential storing Cascading FIFO memory devices for sequential storing

1989-06-29

1990-10-09

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Serial read/write

365 78, 36523003, 365239, 36518902, 377 70, G11C 700

Patent

active

049624830

ABSTRACT:
A FIFO memory device facilitates transfer of data between a host CPU and a peripheral device in one of a number of modes. In one mode, the FIFO memory device functions as two FIFO memories, one for passing data from the host CPU to the peripheral device, and one for passing data to the host CPU from the peripheral device. In another mode, the FIFO memory device functions as a single FIFO which facilitates passing data from the host CPU to the peripheral device or from to peripheral device to the host CPU. The FIFO includes two RAMs addressed by a set of address counters. Of importance, the host CPU can bypass the address counters to directly address each RAM, thereby reading data from or writing data into either RAM regardless of the state of the address counters.

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Electronic Design, Jun. 11, 1987, pp. 77-86, Electronic Design Report "Rich w/Logic, Memory ICs Hone Their Specialties" by Tunick.

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