Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2006-05-09
2006-05-09
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C713S160000
Reexamination Certificate
active
07043600
ABSTRACT:
CAM devices that can be cascaded together to form CAM systems of different sizes are disclosed. The system has one or more clusters of M CAM devices, each device including (M−1) disable connections. Disable signals are used to avoid contention so that one CAM device generates the system output on a shared bus. To reduce pin count, the CAM device of priority N within each cluster has (N−1) of its disable connections programmed as inputs for disable-in signals received from higher-priority CAM devices, and its remaining (M−N) disable connections programmed as outputs for disable-out signals provided to lower-priority CAM devices. Some embodiments include two or more clusters of CAM devices and a controller. In some embodiments, the CAM system works as fast as a single CAM device. Some embodiments impose no architectural limits on the number of CAM devices that can be cascaded together.
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Cheng Paul C.
Chow Nelson L.
Bataille Pierre
Integrated Silison Solution, Inc.
Intellectual Property Law Offices
Roberts Raymond E.
Tsai Sheng-Jen
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