Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-06-09
2001-11-06
Smith, Matthew S. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06314550
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuits, and more specifically to techniques to effectively provide greater number of external pins for input and output of data.
Semiconductor technology continues to improve. This technology allows greater and greater functionality to be provided by a single integrated circuit or “chip.” Signals are input to and output from the chip using external pins or pads. The chip interfaces to external circuitry, possibly on other chips, using the external pins.
The performance of a system depends in part on the amount or rate at which data can be transferred on and off the chip. This transfer rate may be referred to as the data bandwidth. One technique for increasing system performance is to provide more rapid transfer rates. This may be accomplished by improvements in process technology or circuit design. Another technique to increase system performance is to transfer a greater amount of data at one time (or “in parallel”). Therefore, for greater performance, it is important there are many external pins available for input and output of user data.
In an integrated circuit, certain pins are sometimes dedicated to functions other than user data I/O. For example, in a programmable integrated circuit or device such as a PLD or FPGA, some pins may be dedicated to the programming and testing (such as JTAG boundary scan testing) of the device. These dedicated external pin reduce the number of pins available for user I/O. The performance of the chip may be detrimentally affected since not as many user I/O signals may be transferred in parallel. Other programmable devices may include integrated circuits such as microprocessors, coprocessors, microcontrollers, programmable controllers or sequencers, graphics controllers, memories, DRAMs, SRAMs, EPROMs, serial EPROMs, Flash memories, and many others.
Consequently, there is a need for techniques of effectively providing greater number of external pins for input and output to obtain higher performance. Specifically, there is a need for techniques to reduce the number of external pins dedicated to functions other than user I/O, which would make greater number of external pins available for the input and output of user data.
SUMMARY OF THE INVENTION
The present invention is a technique to provide higher system performance by increasing the amount of data that may be transferred in parallel by increasing the available number of external pins available for the input and output of user data (user I/O). One technique is to allow pins to be used for multiple purposes. For example, a dedicated pin may be used for handshaking purpose during configuration of a programmable integrated circuit. This same pin may be used for user I/O during a normal or user mode, or after configuration of the programmable integrated circuit has been completed. By making this dedicated pin available for user I/O, this effectively increases the number of I/O pins.
The technique of the present invention may be software or hardware control, or both. For software control, a user may select a dual-function pin to be used only as user I/O since the function (such as handshaking) is not needed. The user encodes this in a configuration file such as a POF file. Hardware control may be used to automatically release a pin to be used for user I/O after its dedicated purpose has been completed.
Dual-function pin may be especially useful for programmable integrated circuits such as PLDs which can be configured by cascaded programming. During cascaded programming, some pins of the integrated circuit are used for a handshaking function. When programming or configuration is completed, the present inventions allows those handshaking pins to be used as regular I/O pins. Furthermore, the particular programmable integrated may be configured without using cascaded programming. In that case, the handshaking pins are not needed, and the present invention will allow these pins to be used as regular I/O pins. Therefore, an aspect of the present invention is to permit the programming of cascaded programming integrated circuits without the requirement of having dedicated pins for handshaking.
The advantages of providing dual-purpose pins in a programmable integrated circuit include saving device package costs and leaving space for more user I/Os. Overall, this increases the available functionality and value of the devices. There is relatively little cost to implement the circuits to implement dual-mode input and output pins in a programmable integrated circuit.
An aspect of the present invention is the use of an external pin of an integrated circuit to be a configuration pin or an I/O pin. A further aspect to use a pin as a handshaking pin during the configuration of a programmable integrated circuit, and to use the same pin as a user I/O pin when the programmable integrated circuit is not being configured. An aspect of the present invention is the use of circuitry on a programmable integrated circuit to permit at least two modes of operation for an external pin, where one of the modes of operation is related to configuration of the programmable integrated circuit.
In a specific embodiment, the present invention is a method of configuring programmable devices. A source of configuration data is provided. A first pin of a first programmable device is configured to be used to output a handshaking signal. A second pin of a second programmable device is configured to be used to receive the handshaking signal. The first and second programmable devices are configured using the configuration data. Furthermore, after the first programmable device has been configured, the first pin is permitted to be used as a user I/O pin.
In a further embodiment, the present invention is a programmable integrated circuit including first circuitry to configure a first pin as a configuration input pin in a first state and a first user I/O pin in a second state. There is second circuitry to configure a second pin as a configuration output pin in the first state and a second user I/O pin in the second state.
The first circuitry may include a NOR gate having a first input coupled to the first pin and a second input coupled to a state signal configuring the first pin will be in the first or second state; an input buffer coupled to the first pin; and an output buffer coupled to the first pin. The second circuitry may include a multiplexer having a first input coupled to a configuration output logic circuit and a second input coupled to a user mode output circuit; and a tristate buffer coupled between an output of the multiplexer and the second pin.
In a still further embodiment, the present invention includes a method of configuring programmable devices. A first programmable device with a first pin configurable as a special purpose pin or a user I/O pin is provided. A second programmable device with a second pin configurable as a special purpose pin or a user I/O pin is provided. During a first mode, the first pin is configured to be a special purpose pin to output a handshaking signal. During the first mode, the second pin is configured as a special purpose pin to receive the handshaking signal from the first pin. The first and second programmable devices are configured. In a second mode, the first pin is configured to be a user I/O pin. In a second mode, the second pin is configured to be a user I/O pin.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.
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Huang Khai
Nguyen Khai
Sung Chiakang
Wang Bonnie
Wang Xiaobao
Altera Corporation
Siek Vuthe
Smith Matthew S.
Townsend and Townsend / and Crew LLP
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