Cascaded pass-gate test circuit with interposed split-output...

Details Cascaded pass-gate test circuit with interposed split-output... Cascaded pass-gate test circuit with interposed split-output...

2008-01-29

2008-01-29

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S081000, C326S087000, C326S113000, C331S057000

Reexamination Certificate

active

07323908

ABSTRACT:
A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

REFERENCES:
patent: 6188293 (2001-02-01), Miyagi et al.
patent: 6958659 (2005-10-01), Nakajima
patent: 7071736 (2006-07-01), Wikstrom
patent: 7190233 (2007-03-01), Bhushan et al.

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