Cascaded jitter frequency shifting Δ-Σ modulated...

Details Cascaded jitter frequency shifting Δ-Σ modulated... Cascaded jitter frequency shifting Δ-Σ modulated...

2007-11-20

2007-11-20

Fan, Chieh M. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C375S343000

Reexamination Certificate

active

10424718

ABSTRACT:
The invention provides a synchronizer incorporating a Δ-Σ modulator (i.e. a bit stuffing command generator), coupled in series with a frequency offset measurement block and a frequency-locked loop, to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, simplifying attenuation of the jitter energy when the output data stream is desynchronized (demapped). Placement of the Δ-Σ modulator outside the frequency-locked loop allows selectable adjustment of the frequency offset measurement block's frequency. A mapper incorporating the Δ-Σ modulator interprets the pulse train output by the Δ-Σ modulator as stuff
ull/de-stuff commands.

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Tom A.D. Riley, Miles A. Copeland and Tad A. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis,” IEEE Journal of Solid-State Circuits Vol. 28, No. 5, May 1993, pp. 553-559.

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