Cascaded gate-driven ESD clamp

Details Cascaded gate-driven ESD clamp Cascaded gate-driven ESD clamp

2007-05-22

2007-05-22

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Electric charge generating or conducting means

C361S111000, C361S056000, C361S091100

Reexamination Certificate

active

10866453

ABSTRACT:
A method is provided for semiconductor ESD protection in a mixed voltage device using a cascaded gate driven NMOS clamp circuit. Use of a bias circuit allows for an external I/O signal to have a voltage higher than the internal circuit power supply voltage so that a proper trigger level is provided in reference to an external power supply reference. A cascaded gate NMOS clamp circuit dissipates charge from an ESD event from the higher external I/O signal level without interfering with the normal operation of the internal or “core” circuits.

REFERENCES:
patent: 6002568 (1999-12-01), Ker et al.
patent: 6249410 (2001-06-01), Ker et al.
patent: 6671153 (2003-12-01), Ker et al.
patent: 6674622 (2004-01-01), Yu et al.
patent: 6954098 (2005-10-01), Hsu et al.
patent: 7009229 (2006-03-01), Lin et al.

Affiliated with

Also associated with

Rating

Cascaded gate-driven ESD clamp does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cascaded gate-driven ESD clamp, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cascaded gate-driven ESD clamp will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3824743