Cascade wake-up circuit preventing power noise in memory device

Details Cascade wake-up circuit preventing power noise in memory device Cascade wake-up circuit preventing power noise in memory device

2007-02-08

2008-08-19

Phung, Anh (Department: 2824)

Static information storage and retrieval

Powering

Data preservation

C365S194000

Reexamination Certificate

active

07414911

ABSTRACT:
A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.

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