Cascade map decoder and method

Details Cascade map decoder and method Cascade map decoder and method

2006-03-28

2006-03-28

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S755000

Reexamination Certificate

active

07020827

ABSTRACT:
MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and deinterleaver where the MAP decoders generate extrinsic information for iterations. The cascade architecture limits the required number of max* blocks which compute the logarithm of a sum of exponentials as part of the BCJR method.

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patent: 6675342 (2004-01-01), Yagyu
Design of Viterbi Decoders with In-Place State Metric Update and Hybrid Traceback Processing; Ching-Won Wang et al.; Conference Proceedings; Sep. 26, 2001; pp. 5-15.
A Unified Approach to The Viterbi Algorithm State Metric Update for Shift Register Processes; Black, P. J. et al.; Proceedings of the International Conference on Acoutics, Speech and Signal Processing; Mar. 23, 1992; pp. 629-632.
A Turbo Code Tutorial; Ryan, T. E.; Proc. IEEE Global Telecommunications Conference; Nov. 3, 2001; pp. 1-9.

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