Cascadable first-in, first-out memory

Details Cascadable first-in, first-out memory Cascadable first-in, first-out memory

1987-05-29

1989-06-13

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Serial read/write

365 78, 365236, 36518901, 36518908, G11C 700, G11C 800, G11C 1900

Patent

active

048398667

ABSTRACT:
A cascadable first-in, first-out memory unit (11, 12, 13) has a load/unload control (152) for write-addressing and read-addressing selected memory locations within its memory array (82). A write pointer (110, 112, 120) keeps track of the number of write operations that have occurred in the selected memory unit, and a read pointer (130, 132, 142) does the same for the number of read operations. When the number of write operations performed since a last reset pulse (416) equals the number of memory locations in the memory array (82), write control passes to the next succeeding FIFO memory unit by a descending transition of an output control signal (444). Read control is passed to the subsequent FIFO by an ascending transition (470) of the same output control signal. Combination first load, master reset and output control circuitry (54-58, 192) is provided to select the first memory unit (11) for read and write operations, and to disable the outputs (18) of all of the FIFO memory units independent of the master reset signal (55).

REFERENCES:
patent: 4507760 (1985-03-01), Fraser
patent: 4694426 (1987-09-01), Mason

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