Carry logic design having simplified timing modeling for a...

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S041000, C708S700000

Reexamination Certificate

active

06847228

ABSTRACT:
A configurable logic block (CLB) slice is provided that includes a single path for a carry input signal to propagate through the CLB slice as a carry output signal. This single path includes a multiplexer that is configured to receive the input signals (including the carry input signal) and provides an output signal that can be routed as the carry output signal. A driver circuit can be coupled to the output terminal of the multiplexer, thereby improving the drive of the single path. A separate path is provided in parallel with the first multiplexer path, thereby enabling the carry input signal to be applied to exclusive OR gates within the CLB slice, or to be provided as an intermediate carry output signal. The single path provides a relatively fast and consistent manner of routing the carry input signal through the CLB slice as the carry output signal. The first and second paths accommodate a carry initialization signal as well as an intermediate carry input signal.

REFERENCES:
patent: 5416367 (1995-05-01), Chan et al.
patent: 5629886 (1997-05-01), New
patent: 5724276 (1998-03-01), Rose et al.
patent: 5744995 (1998-04-01), Young
Xilinx, Inc., “Virtex -II 1.5 V Field Programmable Gate Arrays,” Virtex-II Platform FPGA Handbook, Dec. 6, 2000, pp. 46-53, , available from Xilinx, Inc. located at 2100 Logic Drive, San Jose, CA 95124.

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