Carry chain standard cell with charge sharing reduction...

Details Carry chain standard cell with charge sharing reduction... Carry chain standard cell with charge sharing reduction...

1999-03-23

2002-04-02

Smith, Matthew S. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06367059

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to an integrated circuit design and methods for making the integrated circuit design that can be implemented as a robust high performance standard cell to be used by a synthesis tool.
2. Description of the Related Art
In the design of semiconductor integrated circuits, circuit designers commonly utilize what are known as “standard cells” to achieve a particular circuit response. Standard cells are essentially pre-designed layouts of transistors that are wired to perform a certain type of logical function. By way of example, a company, such as Artisan Components, Inc. of Sunnyvale, Calif., designs standard cell libraries incorporating many different types of standard cells, each for performing a specific type of logical operation or operations. The standard cells of the standard cell library are then used by integrated circuit design engineers in conjunction with modeling software to produce a larger scale circuit design that meets a particular specification.
A popular and most commonly used modeling software is a hardware description language (HDL) named “Verilog” (IEEE Verilog Standard 1364, 1995). Using Verilog as a synthesis tool, designers are able to describe each component of an integrated circuit in terms of its functional behavior as well as its implementation. Once a circuit design using Verilog is complete, the Verilog code is synthesized to generate what is referred to as a “netlist.” A netlist is essentially a list of “nets,” which specify components (i.e., standard cells) and their interconnections which are designed to meet the circuit design's performance constraints.
The actual placement plan of the standard cells on silicon and the topography of wiring is reserved for a subsequent “layout” stage. In the layout stage, another software tool, commonly referred to as “place and route” software, is used to design the actual wiring that will ultimately interconnect the standard cells together. To do this, each standard cell typically has one or more pins for interconnection with pins of other standard cells. The netlist therefore defines the connectivity between pins of the various standard cells of an integrated circuit device.
Although the design of integrated circuits using specialized software has greatly simplified the design process, this simplicity does not come without a price. For instance, there are several types of high performance circuits that if implemented as standard cells, may cause more harm than good. That is, because standard cells are designed in isolation, i.e., as a single cell that is part of a larger library of standard cells, it is rare and nearly impossible to anticipate when an improper logical interaction will occur between standard cells. Of course, this problem can be overcome if the circuit design was custom designed without the use of a synthesis tool. This would therefore defeat the simplicity of the design process that is afforded by a synthesis tool.
This problem is most prevalent in situations where the standard cell is for a high performance circuit. By way of example, a carry chain (which is commonly used in adders) can be said to be a high performance circuit, which can pose a threat to other logical circuits of adjoining standard cells. The threat posed by the carry chain is that of “charge sharing.” Charge sharing is known to occur when circuitry of adjoining standard cells overwhelm certain input nodes of the carry chain, which would then cause the overwhelming charge to be improperly fed back out to the logic circuitry of the adjoining standard cells. As should be apparent to those skilled in the art, charge sharing in high performance logic designs can have the unfortunate ramification of disrupting the performance of the entire design. This would of course result in substantial losses in re-design time and lost revenues.
To facilitate understanding of the aforementioned problems,
FIG. 1A
illustrates a block diagram
100
of a ripple carry adder. The ripple carry adder includes a propagate/generate block
102
that is configured to generate a plurality of propagate and generate signals. Propagate and generate blocks are well known to those skilled in the art. In the ripple carry adder, a carry chain
104
is implemented to receive the plurality of propagate and generate signals. The carry chain
104
is further configured to receive a carry-in signal (Cin), and output a carry-out signal (Cout). To complete the arithmetic addition operation, a final sum block
106
is implemented to generate the appropriate summation information of the ripple carry adder
100
. The final sum block
106
will generate the final sum using the following Equation 1.
Final Sum=po XOR Co&phgr;  Equation (1)
As is well known, conventional carry chains, such as carry chain
104
are also circuits that introduce a substantial amount of delay during the ripple carry addition operations. To illustrate the type of delays associated with carry chains,
FIG. 1B
provides an example of a multi-bit carry chain having a plurality of a multiplexers
105
. Each multiplexer
105
is configured to receive as inputs a generate signal (i.e., g
0
), and a carry-in (i.e., Cin) signal. The propagate signal (i.e., p
0
) is provided as a select to each of the multiplexers
105
.
If propagate equals a logical one, the carry chain
104
will be “propagating” the carry into each of the bits slices of the carry chain. When propagate is set equal to a logical zero, the carry chain will be “generating” and the generate signal will be passed through each of the multiplexers
105
.
As mentioned above, if the carry chain
104
is implemented as a standard cell, the synthesizing tool may place the carry chain at any location in a design without investigating the possibly of having adverse functional consequences relative to the functionality of other logic circuits of other standard cells. Take for example the Cin and g
0
inputs to the first multiplexer
105
. If a weak driver were connected to the Cin terminal and a strong driver were connected to the g
0
terminal, there may be circumstances where the p
0
(select) has a slow ramping transition. Under this scenario, depending upon the implementation of the MUX, the strong driver connected to the g
0
terminal could overwhelm the weak driver connected to the Cin terminal. This would therefore cause charge sharing, which has the unfortunate consequence of triggering improper logical responses in circuitry of other standard cells.
A further problem with conventional carry chain designs, such as that of
FIG. 1B
, is that a substantial amount of delay is introduced at each bit slice of the multi-bit carry chain
104
. By way of example, at each multiplexer
105
, there will be a two-gate delay. The two-gate delay is then multiplied by the number of bits in the carry chain to provide the final gate delay of the carry chain. This of course will have the downside of severely hampering the performance of the carry chain function and the associated arithmetic addition.
In view of the foregoing, there is a need for a high performance circuit design that is robust enough to be integrated into a standard cell of a standard cell library. The needed high performance circuit design should also be capable of preventing charge sharing with the circuitry of other standard cells that may be integrated together to form a larger scale integrated circuit design.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing high performance and robust multi-bit standard cell circuitry and methods for designing the circuitry. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a computer readable media, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a standard cell architecture is disclosed. The standard cell

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