Carrier having daisy chain of self timed memory chips

Details Carrier having daisy chain of self timed memory chips Carrier having daisy chain of self timed memory chips

2006-07-26

2010-02-09

Peugh, Brian R (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S104000, C710S305000

Reexamination Certificate

active

07660940

ABSTRACT:
A carrier having at least one self timed memory chip in a daisy chain of memory chips. A first carrier has at least a portion of a daisy chain of memory chips attached to the first carrier. An address/command bus input on the first carrier carries an address/command word to a first memory chip in the daisy chain of memory chips. If the first memory chip determines that the address/command word is not directed to the first memory chip, the first memory chip re-drives the address/command word to a second memory chip in the daisy chain of memory chips using a point to point address/command bus link. If there are no more memory chips on the first carrier, the address/command word is re-driven to an address/command bus off-carrier connector. An array on a memory chip has an access time dynamically determined by how fast the array can be accessed.

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