Carrier and system for testing bumped semiconductor components

Details Carrier and system for testing bumped semiconductor components Carrier and system for testing bumped semiconductor components

1997-07-03

2000-03-21

Ballato, Josie

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324758, 324754, 324765, G01R 3102

Patent

active

060407026

ABSTRACT:
A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.

REFERENCES:
patent: 4554505 (1985-11-01), Zachry
patent: 4760335 (1988-07-01), Lindberg
patent: 4937653 (1990-06-01), Blonder et al.
patent: 5006792 (1991-04-01), Malhi et al.
patent: 5046239 (1991-09-01), Miller et al.
patent: 5073117 (1991-12-01), Malhi et al.
patent: 5088190 (1992-02-01), Malhi et al.
patent: 5123850 (1992-06-01), Elder et al.
patent: 5196726 (1993-03-01), Nishiguichi et al.
patent: 5289631 (1994-03-01), Koopman et al.
patent: 5302891 (1994-04-01), Wood et al.
patent: 5322446 (1994-06-01), Cearley-Cabbiness
patent: 5329423 (1994-07-01), Scholz
patent: 5341564 (1994-08-01), Akhavain et al.
patent: 5367253 (1994-11-01), Wood et al.
patent: 5389873 (1995-02-01), Ishii et al.
patent: 5397245 (1995-03-01), Roebuck et al.
patent: 5408190 (1995-04-01), Wood et al.
patent: 5414372 (1995-05-01), Levy
patent: 5420520 (1995-05-01), Anschel et al.
patent: 5451165 (1995-09-01), Cearley-Cabbiness
patent: 5453701 (1995-09-01), Jensen et al.
patent: 5456404 (1995-10-01), Robinette, Jr. et al.
patent: 5481205 (1996-01-01), Frye et al.
patent: 5483174 (1996-01-01), Hembree et al.
patent: 5483741 (1996-01-01), Akram et al.
patent: 5495179 (1996-02-01), Wood et al.
patent: 5500605 (1996-03-01), Chang
patent: 5517125 (1996-05-01), Posedel et al.
patent: 5519332 (1996-05-01), Wood et al.
patent: 5530376 (1996-06-01), Lim et al.
patent: 5534785 (1996-07-01), Yoshiazaki et al.
patent: 5541525 (1996-07-01), Wood et al.
patent: 5543725 (1996-08-01), Lim et al.
patent: 5559444 (1996-09-01), Farnworth et al.
patent: 5578934 (1996-11-01), Wood et al.
patent: 5581195 (1996-12-01), Lee et al.
patent: 5592736 (1997-01-01), Akram et al.
patent: 5604445 (1997-02-01), Desai et al.
patent: 5607818 (1997-03-01), Akram et al.
patent: 5625298 (1997-04-01), Hirano et al.
patent: 5629630 (1997-05-01), Thompson et al.
patent: 5633122 (1997-05-01), Tuttle
patent: 5634267 (1997-06-01), Farnworth et al.
patent: 5678301 (1997-10-01), Gochnour et al.
patent: 5739050 (1998-04-01), Farnworth
patent: 5756370 (1998-05-01), Farnworth et al.
patent: 5783461 (1998-07-01), Hembree
patent: 5801452 (1998-09-01), Farnworth et al.
patent: 5815000 (1998-09-01), Farnworth et al.
patent: 5915755 (1999-06-01), Gochnour et al.
patent: 5915977 (1999-06-01), Hembree et al.
patent: 5931685 (1999-08-01), Hembree et al.
patent: 5962921 (1999-10-01), Farnworth et al.
EIAJ/Area Array Subcommittee/Memory CSP WG, San Diego, CA, Jun. 1995, technical disclosure bulletin.
Mul, Gary K. et al., "Design Optimization for C4 Die Burn-in and Test Carrier/Socket Assembly (with Statistical Considerations)", The International Journal of Microcircuits and Electronic Packaging, vol. 19, No. 2, Second Quarter 1996, pp. 128-137. No month available.
Chip Scale Review, published by Tessera Inc., San Jose, CA, May 1997. No month available.

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