Carbon doped oxide deposition

Details Carbon doped oxide deposition Carbon doped oxide deposition

2001-10-05

2004-01-13

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S783000

Reexamination Certificate

active

06677253

ABSTRACT:

BACKGROUND
The present invention relates to semiconductor layer deposition. In particular, the present invention relates to carbon doped oxide deposition.
BACKGROUND OF THE RELATED ART
In the fabrication of semiconductor devices, layers of varying purposes are formed on a semiconductor substrate. One such layer, an inter-layer dielectric ILD), is deposited and patterned to isolate and support capacitor features such as parallel conductive metal lines. As semiconductor devices and device features decrease in size, the distance between such conductive lines
275
, as shown in
FIG. 2C
, correspondingly decreases. All other factors remaining constant, this results in a higher capacitance (C). For example, given the parallel conductive lines
275
described, capacitance (C) can be viewed as
k
⁢
 
⁢
ϵ
⁢
 
⁢
A
d
where (d) is the distance between the conductive lines
275
, (A), the area of each conductive line interface, (&egr;), the permeability of the ILD, and (k), the dielectric constant (a factor of how much effect the ILD material has on capacitor value).
It can be seen from the above equation that, all other factors remaining constant, as the distance (d) decreases, the capacitance (C) of the system increases. Unfortunately, as capacitance (C) increases so does signal transmission time. Other problems, such as power dissipation and increased cross-talk can also occur. Therefore, reduced capacitance (C) is sought.
The dielectric constant (k) noted above has no units of measure. For example, where the dielectric is of a vacuum or air, the dielectric constant (k) is about equal to 1, having no effect on capacitance. However, most intra-layer dielectric materials have a degree of polarity with a dielectric constant (k) above 1. For example, silicon dioxide, a common ILD material, has a dielectric constant generally exceeding about 4. Due to the decreasing size of semiconductor features (e.g., reduced distance (d) leading to increased capacitance (C)), efforts have recently been made to reduce the dielectric constant (k) of the ILD as a means by which to reduce capacitance (C). That is, where capacitance (C) is
k
⁢
 
⁢
ϵ
⁢
 
⁢
A
d
and all other factors remaining constant, reduction of the dielectric constant (k) can reduce capacitance (C).
Low dielectric constant (k) materials (i.e. ‘low k’ materials), such as fluorinated silica glass (FSG), SiLK™, and carbon doped oxides (CDO's) have been used to form the ILD, thereby reducing capacitance (C). However, the deposition of ‘low k’ materials includes a problem of low deposition rate leading to increased semiconductor processing times, also referred to as low thurput.


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Weber, et al, D., “Impact of substituting SiO ILD by low k materials into AICu Rie metallization”, Infineon Technologies AG, Konigsbruckerstrafe 180, D-01099 Dresden Germany, Current Address : Infineon Technologies, Inc. IBM Semiconductor Research and Development Center, Hopewell Junction, NY 12533, USA.

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