Carbon doped epitaxial layer for high speed CB-CMOS

Details Carbon doped epitaxial layer for high speed CB-CMOS Carbon doped epitaxial layer for high speed CB-CMOS

2001-04-11

2003-06-10

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Fluid growth from gaseous state combined with subsequent...

C438S503000, C438S203000, C438S322000, C438S481000, C438S542000

Reexamination Certificate

active

06576535

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to a high speed complementary bipolar/CMOS fabrication process, and more specifically to forming a silicon epitaxial layer in a PNP transistor having carbon incorporated therein to impede boron up-diffusion from lower heavily boron-doped buried layers into upper PNP structures.
2. State of the Art
Those skilled in the art know that it is difficult to provide a process for fabricating an epitaxial silicon layer that is satisfactory for use in a high speed complementary bipolar/CMOS process (“CB-CMOS”). In such a process, a very thin, lightly doped N-type epitaxial silicon layer must be grown on a silicon wafer including a P
−
type substrate having pre-formed P
+
boron-doped buried layers and pre-formed N
+
arsenic-doped buried layers. In a conventional CB-CMOS process, the epitaxial silicon layer is doped lightly in-situ with arsenic to a concentration of approximately 2×10
15
cm
−1
to achieve an optimal combination of characteristics for NPN, PNP and CMOS transistors to be formed. After the epitaxial deposition, the collector regions of the PNP and NPN transistors and the CMOS “wells” are further doped by a combination of low energy and high energy boron or phosphorous implants with energies and doses tailored to the needs of various “families” of devices. During conventional epitaxial growth and subsequent conventional thermal processing, dopant ions from both the P-type buried layers and the N-type buried layers previously formed in the substrate, such as boron and arsenic respectively, up-diffuse into corresponding portions of the epitaxial layer. This updiffusion is undesirable because it reduces the useful portions of the collector regions of the transistors, thereby reducing the cutoff frequencies and transistor switching speeds, and increasing the collector-to-emitter saturation voltage and power dissipation.
Conventionally, in “complementary” bipolar CMOS structures, it is desirable to have NPN and PNP transistors which have matched characteristics. One problem experienced in matching the characteristics of the NPN and PNP transistors, however, is that the P
+
and N
+
buried layers of the respective NPN and PNP transistors up-diffuse at significantly different rates, resulting in mismatches. Since the up-diffusion of a P
+
buried layer accelerates more rapidly than an N
+
layer with respect to temperature, differences in the thicknesses of the collectors of the PNP transistors and the NPN transistors are conventionally minimized by keeping the “Dt” of all high temperature process steps as low as possible. “Dt” is a term referring to the cumulative amount of time and heat that the wafer is subjected to high temperatures, usually exceeding 1000° C., after the epitaxial layer has been deposited. The deep double implants used to form the collectors of the required depth for the NPN and PNP transistors, respectively, eliminate the need for high Dt diffusions after the formation of the epitaxial layer. One drawback associated with the large differential dopant diffusivity of arsenic buried layers and boron buried layers, however, remains even for “low Dt processing.” For very low Dt processes, achieving the desirable PNP collector often results in producing an undesirable lightly doped N type subregion where an NPN collector region meets the N
+
buried layer.
A conventional approach to addressing boron up-diffusion in CB-CMOS structures involves one or more of the following processes: 1) creating a much thicker epitaxial layer than otherwise would be necessary for meeting the NPN breakdown requirements; 2) significantly reducing the doping levels for P
+
buried layers compared as compared to the doping levels for N
+
buried layers; 3) including a phosphorus, rather than arsenic, doped N
+
buried layer; and 4) offering lateral PNP structures instead of vertical PNP structures. However, each of these processes improves the required breakdown characteristics of the PNP structures at the expense of the NPN or PNP device characteristics. An excessively thick epitaxial layer leads to a higher collector resistance of both NPN and PNP transistors. A thicker epitaxial layer also forces the use of a higher Dt in subsequent processing, which produces larger lateral device dimensions and larger junction capacitances. The light doping level of boron in the P
+
buried layer adds to its already large resistance caused by the combination of low carrier concentration and low mobility of holes. In summary, NPN and PNP structures made using conventional approaches still are not well matched. They result in slowed operating responses and much larger area than necessary or desirable.
Carbon has been incorporated into SiGe epitaxial layers to suppress out diffusion of boron from the bases of rf bipolar transistor, as described in “Suppression of Boron Outdiffusion in SiGe HBT by Carbon Incorporation”, by L. D. Lanzerotti et al., IDEM Technical Digest, pp. 249-252, 1986 and in “the Effect of Carbon Incorporation on SiGe Heterobipolar Transistor Performance and Process Margin”, IDEM Technical Digest, pp. 80-86, 1987.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of making a CB-CMOS device in which boron up-diffusion from a buried layer into an epitaxial layer of the CB-CMOS device is suppressed.
It is another object of the invention to provide a layer within the CB-CMOS device which includes sufficient carbon to significantly suppress boron up-diffusion.
It is yet another object of the invention to provide a CMOS structure which includes a carbon-doped epitaxial layer between buried layers and other epitaxial layers to suppress boron up-diffusion from the buried layers into the other epitaxial layers.
It is still yet another object of the invention to provide an improved epitaxial process for a CB-CMOS to suppress the up-diffusivity of boron without sacrificing speed or size characteristics.
It is still another object of the invention to provide a method of fabricating a high speed CB-CMOS device which includes at least two carbon-doped epitaxial layers, one between the buried layers and the epitaxial layers, and one on the final epitaxial layer to reduce dopant diffusivities within a transistor body between base and emitter.
The present invention provides a method for fabricating a high speed CB-CMOS device by incorporating a carbon-doped epitaxial layer to suppress boron up-diffusion from lower heavily boron-doped buried layers into upper structures. According to an embodiment of the invention, an epitaxial layer is formed on a P type silicon substrate in which a plurality of P
+
buried layer regions, a plurality of N
+
buried layer regions, and a P
+
field layer region occupying most of the substrate surface are diffused. The substrate wafer is loaded in a reactor with a carrier gas and pre-baked at a temperature of approximately 850° C. The temperature is then gradually increased to approximately 1050° C. and subjected to a high temperature bake cycle. A thin carbon-doped epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at approximately 1080° C. Then an N
−
epitaxial layer is deposited on the carbon-doped epitaxial cap layer at approximately 1080° C.
According to a second embodiment of the invention, the process further includes the steps of low temperature baking the wafers and increasing the temperature to approximately 1050° C., both in the presence of N
+
gas. The process also further includes, between the steps of the high temperature gas purge cycle and deposition of the N
−
epitaxial layer, depositing an intrinsic epitaxial layer on the carbon-doped epitaxial cap and performing an additional high temperature gas purge cycle, both at approximately 1080° C. The addition of these process steps increases the ability of the structure to suppress boron auto-doping during the epitaxial layer d

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