Capturing data and crossing clock domains in the absence of...

Details Capturing data and crossing clock domains in the absence of... Capturing data and crossing clock domains in the absence of...

2007-02-27

2007-02-27

Tran, Khanh (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C711S111000

Reexamination Certificate

active

10327727

ABSTRACT:
Data, such as data received by a memory I/O from a memory unit in a DDR SDRAM system, is captured using a trigger signal, which may be a non free-running clock signal such as a DQS signal in a DDR SDRAM system, and is transferred to a host system, which may be part of an ASIC, using the host system's clock. The memory I/O includes a data capture register that latches the data received from the memory unit using DQS. The memory I/O also includes a FIFO buffer that latches the data output by the data capture register using a delayed version of DQS. A single edge of the delayed DQS is available to the FIFO for latching each set of data that corresponds to a single pulse of DQS. The FIFO transfers the data to the host system using the host system's clock, which represents a different clock domain than DQS.

REFERENCES:
patent: 6330645 (2001-12-01), Harriman
patent: 6603706 (2003-08-01), Nystuen et al.
patent: 6819730 (2004-11-01), He
patent: 6918016 (2005-07-01), Magro
patent: 2004/0012577 (2004-01-01), Naegle et al.

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