Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-07-31
2010-10-12
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C451S064000, C451S461000, C156S345120, C414S935000, C438S690000
Reexamination Certificate
active
07811925
ABSTRACT:
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.
REFERENCES:
patent: 4002778 (1977-01-01), Bellis et al.
patent: 4181760 (1980-01-01), Feldstein
patent: 4311551 (1982-01-01), Sykes
patent: 4737446 (1988-04-01), Cohen et al.
patent: 4981725 (1991-01-01), Nuzzi et al.
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5318803 (1994-06-01), Bickford et al.
patent: 5380560 (1995-01-01), Kaja et al.
patent: 5382447 (1995-01-01), Kaja et al.
patent: 5486234 (1996-01-01), Contolini et al.
patent: 5576052 (1996-11-01), Arledge et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5770095 (1998-06-01), Sasaki et al.
patent: 5891513 (1999-04-01), Dubin et al.
patent: 5897375 (1999-04-01), Watts et al.
patent: 5913147 (1999-06-01), Dubin et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5972192 (1999-10-01), Dubin et al.
patent: 6065424 (2000-05-01), Shacham-Diamond et al.
patent: 6136707 (2000-10-01), Cohen
patent: 6174353 (2001-01-01), Yuan et al.
patent: 6184124 (2001-02-01), Hasegawa et al.
patent: 6197181 (2001-03-01), Chen
patent: 6197364 (2001-03-01), Paunovic et al.
patent: 6270619 (2001-08-01), Suzuki et al.
patent: 6309981 (2001-10-01), Mayer et al.
patent: 6329284 (2001-12-01), Maekawa
patent: 6342733 (2002-01-01), Hu et al.
patent: 6355153 (2002-03-01), Uzoh et al.
patent: 6398855 (2002-06-01), Palmans et al.
patent: 6537416 (2003-03-01), Feng et al.
patent: 6586342 (2003-07-01), Mayer et al.
patent: 6645567 (2003-11-01), Mayer et al.
patent: 6664122 (2003-12-01), Andryuschenko et al.
patent: 6692546 (2004-02-01), Ma et al.
patent: 6692873 (2004-02-01), Park
patent: 6713122 (2004-03-01), Mayer et al.
patent: 6716753 (2004-04-01), Shue et al.
patent: 6775907 (2004-08-01), Boyko et al.
patent: 6815349 (2004-11-01), Minshall et al.
patent: 6884724 (2005-04-01), Hsu et al.
patent: 6887776 (2005-05-01), Shang et al.
patent: 7262504 (2005-07-01), Cheng et al.
patent: 7285494 (2005-07-01), Cheng et al.
patent: 6975032 (2005-12-01), Chen et al.
patent: 7008871 (2006-03-01), Andricacos et al.
patent: 7049234 (2006-05-01), Cheng et al.
patent: 7056648 (2006-06-01), Cooper et al.
patent: 7124386 (2006-10-01), Smith et al.
patent: 7217649 (2007-05-01), Bailey et al.
patent: 7338908 (2008-03-01), Koos et al.
patent: 2001/0038448 (2001-11-01), Jun et al.
patent: 2002/0084529 (2002-07-01), Dubin et al.
patent: 2003/0003711 (2003-01-01), Modak
patent: 2003/0059538 (2003-03-01), Chung et al.
patent: 2003/0075808 (2003-04-01), Inoue et al.
patent: 2003/0176049 (2003-09-01), Hegde et al.
patent: 2003/0190426 (2003-10-01), Padhi et al.
patent: 2003/0203616 (2003-10-01), Chung et al.
patent: 2004/0065540 (2004-04-01), Chebiam et al.
patent: 2004/0253740 (2004-12-01), Shalyt et al.
patent: 2005/0074967 (2005-04-01), Kondo et al.
patent: 2005/0158985 (2005-07-01), Chen et al.
patent: 2005/0250339 (2005-11-01), Shea et al.
patent: 2005/0266265 (2005-12-01), Cheng et al.
patent: 2006/0205204 (2006-09-01), Beck
patent: 02111883 (1990-04-01), None
patent: 03122266 (1991-05-01), None
patent: 99/47731 (1999-09-01), None
U.S. Office Action mailed Jan. 23, 2007, from U.S. Appl. No. 11/251,353.
Andryuschenko et al., “Electroless and Electrolytic Seed Repair Effects on Damascene Feature Fill,” Proceedings of International Interconnect Tech. Conf., San Francisco CA., Jun. 4-6, 2001, pp. 33-35.
Chen et al., “ECD Seed Layer for Inlaid Copper Metallisation,” Semiconductor Fabtech—12thEdition, 5 Pages, Jul. 2000.
Ken M. Takahashi, “Electroplating Copper into Resistive Barrier Films,” Journal of the Electrochemical Society, 147 (4) 1417-1417 (2000).
T.P. Moffat et al., “Superconformal Electrodeposition of Copper in 500-90 nm Features,” Journal of the Electrochemical Society, 147 (12) 4524-4535 (2000).
Ritzdorf et al., “Electrochemically Deposited Copper,” Conference Proceedings ULSI XV 2000, Materials Research Society, 101-107.
Reid et al., “Optimization of Damascene Feature Fill for Copper Electroplating Process,” Shipley Company, IITC 1999, 3 Pages.
Reid et al., “Copper PVD and Electroplating,” Solid State Technology, Jul. 2000, www.solid-state.com, 86-103.
Reid et al., “Factors Influencing Fill of IC Features Using Electroplated Copper,” Adv Met Conf Proc 1999, MRS 10 Pages, (2000).
Shacham-Diamond et al., “Copper Electroless Deposition Technology for Ultr-Large-Scale-Integration (ULSI) Metallization,” Microelectronic Engineering 33 (1997) 47-58.
Hu et al., “Effects of Overlayers on Electromigration Reliability Improvement for Cu/Low K Interconnects,” Presented in the Proceedings of the 42ndAnnual IRPS held Apr. 25-29, 2004, p. v, article published May 28, 2004, 7 pages.
Park et al., “Electroless Layer Plating Process and Apparatus”, Novellus Systems, Inc., U.S. Appl. No. 10/235,420, filed Sep. 30, 2002.
U.S. Office Action dated Sep. 1, 2005 for U.S. Appl. No. 10/235,420.
Sullivan et al, Electrolessly Deposited Diffusion Barriers For Microelectronics, E. J. IBM J Res Develop vol. 42, No. 4 Sep. 1998, 607-620.
T. Itabashi et al., “Electroless Deposited CoWB for Copper Diffusion Barrier Metals,” Hitachi Research Laboratory, IEEE, 2002, 285-287.
Yosi Shacham-Diamand and Sergey Lopatin, “Integrated Electroless Metallization for ULSI,” Elecrochimica Acta, (44 (19999) 3639-3649.
Theoretical Studies on the Electroless Metal Deposition Reaction Mechanism Group, printed from website http://www.appchem.waseda.ac.jp on Jul. 3, 2002. Published prior to the filing of this application. 3 Pages.
Office Action mailed Jul. 27, 2007, from U.S. Appl. No. 11/586,394.
Mayer et al., “Pad-Assisted Electropolishing,” Novellus Systems, Inc., U.S. Appl. No. 11/213,190, filed Aug. 26, 2005.
Mayer et al., “Topography Reduction and Control by Selective Accelerator Removal,” Novellus Systems, Inc., U.S. Appl. No. 11/602,128, filed Nov. 20, 2006.
U.S. Office Action mailed Aug. 16, 2006 from U.S. Appl. No. 10/742,006.
U.S. Final Office Action mailed Jul. 18, 2007 from U.S. Appl. No. 11/251,353.
U.S. Office Action mailed Nov. 30, 2006 from U.S. Appl. No. 10/690,084; 6 pages.
U.S. Office Action mailed Aug. 2, 2007 from U.S. Appl. No. 10/690,084.
Notice of Allowance mailed Oct. 2, 2007 from U.S. Appl. No. 10/690,084.
U.S. Office Action mailed Feb. 8, 2008 from U.S. Appl. No. 11/251,353.
Final Office Action mailed May 13, 2008 from U.S. Appl. No. 11/251,353.
Notice of Allowance mailed May 13, 2008, from U.S. Appl. No. 11/251,353.
U.S. Final Office Action mailed Jun. 12, 2008 from U.S. Appl. No. 11/586,394.
Mori et al., “Metal Capped Cu Interconnection Technology by Chemical Mechanical Polishing,” VMIC Conference, 1996, 487-492.
Hu et al., “Reduced Electromigration of Cu Wires by Surface Coating,” Applied Physics Letters, vol. 81, No. 10, (2002), 1782-1784.
E.G. Colgan, “Selective CVD-W For Capping Damascene Cu Lines,” Thin Solid Films, 262 (1995), 120-123.
Enhanced Copper Metallurgy for BEOL Application, IBM Technical Disclosure Bulletin, vol. 33, No. 5, (1990), 217-218).
U.S. Office Action mailed Nov. 26, 2007 from U.S. Appl. No. 11/586,394.
Eugene J. O'Sullivan, “Electroless Deposition in Microelectronics: New Trend,” (2000) Electrochemical Society Proceeding vol. 99-34, 159-171.
N. Petrov and Y. Shacham-Diamand, “Electrochemica
Kepten Avishai
Mayer Steven T.
Minshall Edmund B.
Reid Jonathan D.
Stowell R. Marshall
Coleman W. David
Novellus Systems Inc.
Weaver Austin Villeneuve & Sampson LLP
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