Capping before barrier-removal IC fabrication method

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21076, C257SE21174

Reexamination Certificate

active

07605082

ABSTRACT:
Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

REFERENCES:
patent: 4002778 (1977-01-01), Bellis et al.
patent: 4181760 (1980-01-01), Feldstein
patent: 4737446 (1988-04-01), Cohen et al.
patent: 4981725 (1991-01-01), Nuzzi et al.
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5318803 (1994-06-01), Bickford et al.
patent: 5380560 (1995-01-01), Kaja et al.
patent: 5382447 (1995-01-01), Kaja et al.
patent: 5486234 (1996-01-01), Contolini et al.
patent: 5576052 (1996-11-01), Arledge et al.
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5770095 (1998-06-01), Sasaki et al.
patent: 5824599 (1998-10-01), Shacham-Diamond et al.
patent: 5891513 (1999-04-01), Dubin et al.
patent: 5897375 (1999-04-01), Watts et al.
patent: 5913147 (1999-06-01), Dubin et al.
patent: 5969422 (1999-10-01), Ting et al.
patent: 5972192 (1999-10-01), Dubin et al.
patent: 6065424 (2000-05-01), Shacham-Diamond et al.
patent: 6136707 (2000-10-01), Cohen
patent: 6174353 (2001-01-01), Yuan et al.
patent: 6184124 (2001-02-01), Hasegawa et al.
patent: 6197181 (2001-03-01), Chen
patent: 6197364 (2001-03-01), Paunovic et al.
patent: 6309981 (2001-10-01), Mayer et al.
patent: 6329284 (2001-12-01), Maekawa
patent: 6342733 (2002-01-01), Hu et al.
patent: 6355153 (2002-03-01), Uzoh et al.
patent: 6398855 (2002-06-01), Palmans et al.
patent: 6537416 (2003-03-01), Mayer et al.
patent: 6586342 (2003-07-01), Mayer et al.
patent: 6645567 (2003-11-01), Chebiam et al.
patent: 6664122 (2003-12-01), Andryuschenko et al.
patent: 6692546 (2004-02-01), Ma et al.
patent: 6692873 (2004-02-01), Park
patent: 6713122 (2004-03-01), Mayer et al.
patent: 6716753 (2004-04-01), Shue et al.
patent: 6775907 (2004-08-01), Boyko et al.
patent: 6815349 (2004-11-01), Minshall et al.
patent: 6884724 (2005-04-01), Hsu et al.
patent: 6887776 (2005-05-01), Shang et al.
patent: 6962873 (2005-11-01), Park
patent: 6975032 (2005-12-01), Chen et al.
patent: 7008871 (2006-03-01), Andricacos et al.
patent: 7049234 (2006-05-01), Cheng et al.
patent: 7056648 (2006-06-01), Cooper et al.
patent: 7262504 (2007-08-01), Cheng et al.
patent: 7285494 (2007-10-01), Cheng et al.
patent: 7338908 (2008-03-01), Koos et al.
patent: 2001/0038448 (2001-11-01), Jun et al.
patent: 2002/0084529 (2002-07-01), Dubin et al.
patent: 2003/0003711 (2003-01-01), Modak
patent: 2003/0059538 (2003-03-01), Chung et al.
patent: 2003/0075808 (2003-04-01), Inoue et al.
patent: 2003/0079526 (2003-05-01), Chung et al.
patent: 2003/0176049 (2003-09-01), Hedge et al.
patent: 2003/0190426 (2003-10-01), Padhi et al.
patent: 2004/0065540 (2004-04-01), Chebiam et al.
patent: 2004/0253740 (2004-12-01), Shalyt et al.
patent: 2005/0074967 (2005-04-01), Kondo et al.
patent: 2005/0158985 (2005-07-01), Chen et al.
patent: 2005/0250339 (2005-11-01), Shea et al.
patent: 2005/0266265 (2005-12-01), Cheng et al.
patent: 2006/0205204 (2006-09-01), Beck
patent: 2 111 883 (1990-04-01), None
patent: 02111883 (1990-04-01), None
patent: 3 122 266 (1991-05-01), None
patent: 03122266 (1991-05-01), None
patent: 99/47731 (1999-09-01), None
SanderKok.com, “Analytical Chemistry”, http://home.planet.nl/˜skok/ttechniques/laboratory/pka—pkb.html.
Andryuschenko et al., “Electroless and Electrolytic Seed Repair Effects on Damascene Feature Fill,” Proceedings of International Interconnect Tech. Conf., San Francisco Ca., Jun. 4-6, 2001, pp. 33-35.
Chen et al., “EDC Seed Layer for Inlaid Copper Metallisation,” Semiconductor Fabtech—12thEdition, 5 Pages, Jul. 2000.
Ken M. Takahashi, “Electroplating Copper into Resistive Barrier Films,” Journal of the Electrochemical Society, 147 (4), 1417-1417 (2000).
O'Sullivan, et al., “Electrolessly Deposited Diffusion Barriers for Microelectronics,” The IBM Journal of Research and Development, vol. 42, No. 5, 1998, 13 pages.
Wolf, Silicon Processing for the VLSI Era, Lattice Press, vol. 3, p. 648.
Eugene J. O″Sullivan, “Electroless Deposition in Microelectronics: New Trend,” Electrochemical Society Proceeding vol. 99-34, 159-171.
T. Itabashi et al., “Electroless Deposited CoWB for Copper Diffusion Barrier Metals,” Hitachi Research Laboratory, IEEE, 2002, 285-287.
N. Petrov and Y. Shacham-Diamand, “Electrochemical Study of the Electroless Deposition of Co(W,P) Barrier Layers for Cu Metallization,” Electrochemical Soc. Proceedings vol. 2000-27, 134-148.
Yosi Shacham-Diamand and Sergey Lopatin, “Integrated Electroless Metallization of ULSI,” Elecrochimica Acta, (44 (19999) 3639-3649.
T.P. Moffat et al., “Superconformal Electrodeposition of Copper in 500-90 nm Features,” Journal of the Electrochemical Society, 147 (12) 4524-4535 (2000).
Ritzdorf et al., “Electrochemically Deposited Copper,” Conference Proceedings ULSI XV 2000, Materials Research Society, 101-107.
Reid et al., “Optimization of Damascene Feature Fill for Copper Electroplating Process,” Shipley Company, IITC 1999, 3 Pages.
Reid et al., “Copper PVD and Electroplating,” Solid State Technology, Jul. 2000, www.solid-state.com, 86-103.
Reid et al., “Factors Influencing Fill of IC Features Using Electroplated Copper,” Adv Met Conf Proc 1999, MRS 10 Pages, (2000).
Shacham-Diamond et al., “Copper Electroless Deposition Technology for Ultr-Large-Scale-Integration (ULSI) Metallization,” Microelectronic Engineering 33 (1997) 47-58.
Hu et al., “Effects of Overlayers on Electromigration Reliability Improvement for Cu/Low K Interconnects,” Presented in the Proceedings of the 42ndAnnual IRPS held Apr. 25-29, 2004, p. v, article published May 28, 2004, 7 Pages.
Mori et al., “Metal Capped Cu Interconnection Technology by Chemical Mechanical Polishing,” VMIC Conference, 1996, 487-492.
Hu et al., “Reduced Electromigration of Cu Wires by Surface Coating,” Applied Physics Letters, vol. 81, No. 10, (2002), 1782-1784.
E.G. Colgan, “Selective CVD-W for Capping Damascene Cu Lines,” Thin Solid Films, 262, (1995), 120-123.
Enhanced Copper Metallurgy for BEOL Application, IBM Technical Disclosure Bulletin, vol. 33, No. 5, (1990), 217-218.
Park et al., “Electroless Layer Plating Process and Apparatus,” U.S. Appl. No. 10/235,420, filed Sep. 30, 2002.
Park et al., “Electroless Layer Plating Process and Apparatus,” U.S. Appl. No. 10/235,420, filed Sep. 30, 2002, Office Action dated Sep. 1, 2005.
Koos et al., “Method for Fabrication of Semiconductor Interconnect Structure with Reduced Capacitance, Leakage Current, and Improved Breakdown Voltage,” U.S. Appl. No. 10/690,084, filed Oct. 20, 2003.
Koos et al., “Method for Fabrication of Semiconductor Interconnect Structure with Reduced Capacitance, Leakage Current, and Improved Breakdown Voltage,” U.S. Appl. No. 10/690,084, filed Oct. 20, 2003, Office Action dated Nov. 5, 2005.
U.S. Office Action mailed Aug. 5, 2005, from U.S. Appl. No. 10/690,084.
Koos, et al., “Method For Fabrication Of Semiconductor Interconnect Structure With Reduced Capacitance, Leakage Current, And Improved Breakdown Voltage” Novellus Systems, Inc., U.S. Appl. No. 10/690,084, filed Oct. 20, 2003, pp. 1-26.
Hu, et al., “Effects of Overlayers on Electromigration Reliability Improvement for Cu/Low K Interconnects”, article published before Oct.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Capping before barrier-removal IC fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Capping before barrier-removal IC fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Capping before barrier-removal IC fabrication method will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4139859

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.