Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-07-17
2009-10-13
Pert, Evan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S347000, C257SE27084, C257SE21409, C438S149000, C438S596000
Reexamination Certificate
active
07602001
ABSTRACT:
This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.
REFERENCES:
patent: 5358879 (1994-10-01), Brady et al.
patent: 5446299 (1995-08-01), Acovic et al.
patent: 5693549 (1997-12-01), Kim
patent: 5714786 (1998-02-01), Gonzalez et al.
patent: 5753947 (1998-05-01), Gonzalez
patent: 6005273 (1999-12-01), Gonzalez et al.
patent: 6090693 (2000-07-01), Gonzalez et al.
patent: 6096596 (2000-08-01), Gonzalez
patent: 6420786 (2002-07-01), Gonzalez et al.
patent: 6632723 (2003-10-01), Watanabe et al.
patent: 6818937 (2004-11-01), Noble et al.
patent: 6888198 (2005-05-01), Krivokapic
patent: 6888770 (2005-05-01), Ikehashi
patent: 6969662 (2005-11-01), Fazan et al.
patent: 7005710 (2006-02-01), Gonzalez et al.
patent: 7027334 (2006-04-01), Ikehashi
patent: 7030436 (2006-04-01), Forbes
patent: 2002/0130378 (2002-09-01), Forbes et al.
patent: 2002/0192911 (2002-12-01), Parke
patent: 2003/0094651 (2003-05-01), Suh
patent: 2004/0061148 (2004-04-01), Hsu
patent: 2004/0197995 (2004-10-01), Lee et al.
patent: 2005/0017240 (2005-01-01), Fazan
patent: 2005/0063224 (2005-03-01), Fazan et al.
patent: 2005/0124130 (2005-06-01), Mathew et al.
patent: 2005/0167751 (2005-08-01), Nakajima et al.
patent: 2006/0083058 (2006-04-01), Ohsawa
patent: 2006/0194410 (2006-08-01), Sugaya
patent: 2007/0001222 (2007-01-01), Orlowski et al.
patent: 2007/0158719 (2007-07-01), Wang
patent: 2008/0061346 (2008-03-01), Tang et al.
patent: WO 2007/014689 (2007-06-01), None
patent: PCT/US2007/019592 (2008-02-01), None
J. Chen et al.,The Enhancement of Gate-Induced-Drain-Leakage(GIDL)Current in Short-Channel SOI MOSFET and its Application in. . . , IEEE Electron Device Letters, vol. 13, No. 11, pp. 572-574 (Nov. 1992).
Y. Choi et al.,Investigation of Gate-Induced Drain Leakage(GIDL)Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and. . . , Jpn. J. Appl. Phys., vol. 42, pp. 2073-2076 (2003).
F. Gonzalez et al.,A dynamic source-drain extension MOSFET using a separately biased conductive spacer,Solid-State Electronics, vol. 46, pp. 1525-1530 (2002).
C. Kuo et al.,A Capacitorless Double-Gate DRAM Cell Design for High Density Applications,IEEE, IEDM, pp. 843-846 (2002).
E. Lusky et al.,Investigation of Channel Hot Electron Injection by Localized Charge-Trapping Nonvolatile Memory Devices,IEEE Transactions on Electron Devices, vol. 51, No. 3, pp. 444-451 (Mar. 2004).
M. Minami et al.,A High Speed and High Reliability MOSFET Utilizing an Auxiliary Gate,1990 Symposium on VLSI Technology, IEEE, pp. 41-42 (1990).
K. Sunouchi et al.,Double LDD Concave(DLC)Structure for Sub-Half Micron MOSFET,IEEE, IEDM, pp. 226-228 (1988).
S. Tiwari et al.,Straddle Gate Transistors: High Ion/IoffTransistors at Short Gate Lengths,IBM Research Article, pp. 26-27 (pre-Mar. 2006).
E. Yoshida et al.,A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage(GIDL)Current for Low-Power and High-Speed. . . , IEEE Transactions on Electron Devices, vol. 53, No. 4, pp. 692-697 (Apr. 2006).
Invitation fo Pay Additional Fees, date of mailing Jan. 14, 2008, including documents considered to be relevant, pp. 1-10.
Fazan et al., “MOSFET design simplifies DRAM”, EE Times, May 13, 2002, 7 pgs.
Hara, “Toshiba cuts capacitor from DRAM cell design”, EE Times, http://www.us.design-reuse.com
ews
ews24,html, Feb. 7, 2002, 2 pgs.
Minami et al., “A Floating Body Cell (FBC) Fully Compatible with 90 nm CMOS Technology (CMOS4) for 128Mb SOI DRAM”, 2005 IEDM Technical Program, 2005, pp. 13.1.1-13.1.4.
Ranica et al., “A One Transistor Cell on Bulk Substrate (IT-Bulk) for Low-Cost & High Density eDRAM”, VLSI Technology, 2004, IEEE, (Jun. 15, 2004), pp. 128-129.
Tanaka et al., “Scalability study on a capacitorless 1T-DRAM: from single-gate PD-SOI to double-gate FinDRAM”, IEDM Technical Digest, IEEE International Electron Devices Meeting, Dec. 13-15, 2004, pp. 37.5-1.37-5.4.
Villaret et al., “Mechanisms of charge modulation in the floating body of triple-well nMOSFET capacitor-less DRAMs”, vol. 72 (1-4), Elsevier Publishers B.V., Apr. 2004, pp. 434-439.
Yoshida et al., “A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory”, IEEE International Electron Devices Meeting, 2003, IEDM '03 Technical Digest, Dec. 8-10, 2003, pp. 37.6.1-37.6.4.
Micro)n Technology, Inc.
Pert Evan
Quinto Kevin
Wells St. John P.S.
LandOfFree
Capacitorless one transistor DRAM cell, integrated circuitry... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Capacitorless one transistor DRAM cell, integrated circuitry..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Capacitorless one transistor DRAM cell, integrated circuitry... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4144123