Capacitorless DRAM on bulk silicon

Details Capacitorless DRAM on bulk silicon Capacitorless DRAM on bulk silicon

2009-04-10

2010-11-09

Garber, Charles D (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S164000, C438S269000, C438S311000, C257SE21320, C257SE21562, C257SE21646

Reexamination Certificate

active

07829399

ABSTRACT:
A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer.

REFERENCES:
patent: 5414287 (1995-05-01), Hong
patent: 5416350 (1995-05-01), Watanabe
patent: 5465249 (1995-11-01), Cooper, Jr. et al.
patent: 5510630 (1996-04-01), Agarwal et al.
patent: 5897351 (1999-04-01), Forbes
patent: 5936274 (1999-08-01), Forbes et al.
patent: 5948162 (1999-09-01), Nakamura
patent: 5972758 (1999-10-01), Liang
patent: 5973356 (1999-10-01), Noble et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6072209 (2000-06-01), Noble et al.
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6124729 (2000-09-01), Noble et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6150687 (2000-11-01), Noble et al.
patent: 6153468 (2000-11-01), Forbes et al.
patent: 6174780 (2001-01-01), Robinson
patent: 6238976 (2001-05-01), Noble et al.
patent: 6245636 (2001-06-01), Maszara
patent: 6246083 (2001-06-01), Noble
patent: 6274913 (2001-08-01), Brigham et al.
patent: 6352864 (2002-03-01), Lee
patent: 6376286 (2002-04-01), Ju
patent: 6429074 (2002-08-01), Lee et al.
patent: 6465846 (2002-10-01), Osanai
patent: 6465852 (2002-10-01), Ju
patent: 6538916 (2003-03-01), Ohsawa
patent: 6599789 (2003-07-01), Abbott et al.
patent: 6617651 (2003-09-01), Ohsawa
patent: 6661042 (2003-12-01), Hsu
patent: 6714436 (2004-03-01), Burnett et al.
patent: 6717205 (2004-04-01), Gratz
patent: 6881994 (2005-04-01), Lee et al.
patent: 6956256 (2005-10-01), Forbes
patent: 7030436 (2006-04-01), Forbes
patent: 7432173 (2008-10-01), Kang et al.
patent: 2002/0038886 (2002-04-01), Mo
patent: 2004/0026749 (2004-02-01), Ohsawa
patent: 2004/0042256 (2004-03-01), Forbes
patent: 2004/0058506 (2004-03-01), Fukuzumi
patent: 2005/0138262 (2005-06-01), Forbes
patent: 2005/0167751 (2005-08-01), Nakajima et al.
patent: 2005/0212033 (2005-09-01), Forbes
patent: 62 296458 (1987-12-01), None
patent: 2000 269460 (2000-09-01), None
Ararwal et al., “SiC Electronics,”International Electron Devices Meeting Technical Digest, 1996, p. 225.
Denton et al., “Fully depleted dual-gated thin-film SOI P-MOSFET's fabricated in SOI islands with an isolated buried polysilicon backgate,”IEEE Electron Device Letters, Nov. 1996, pp. 509-511, vol. 17, No. 11.
Dimitrijev et al., “Charge retention in metal-oxide-semiconductor capacitors on SiC used as nonvolatile-memory elements,”Applied Physics Letters, vol. 80, No. 18, pp. 3421-3423, May 6, 2002.
Fazan et al., “A simple 1-transistor capacitor-less memory cell for high performance embedded DRAMs,” Proceedings of the IEEE Custom Integrated Circuits Conference 2002, pp. 99-102.
Fazan et al., “Capacitor-less 1-transistor DRAM,” IEEE International SOI Conference, 2002, pp. 10-13.
Kallender, P., “Swiss team develops single-transistor SOI DRAM cell,” http://www.eeitmes.com/story/OEG20011016S0099, Oct. 16, 2001.
Ohsawa et al., “A Memory Using One-Transistor Gain Cell on SOI (FBC) with Performance Suitable for Embedded DRAM's” Symposium on VLSI Circuits, Jun. 12-14, 2003, pp. 93-96.
Ohsawa et al., “Memory Design Using a One-Transistor Gain Cell on SOI,”IEEE Journal of Solid-State Circuits, vol. 37, No. 11, pp. 1510-1522, Nov. 2002.
Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI,” IEEE Int. Solid State Circuits Conference, San Francisco, 2002, pp. 152-153.
Yoshida et al., “A design of a capacitorless 1T-DRAM cell using gate-induced drain leakage (GIDL) current for low-power and high-speed embedded memory,”Technical Digest—International Electron Devices Meeting 2003, 2003, IEEE Cat. No. 03CH3747, pp. 913-916.

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