Capacitorless DRAM gain cell

Details Capacitorless DRAM gain cell Capacitorless DRAM gain cell

2002-03-22

2003-05-06

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S181000, C365S182000, C365S230050, C365S185010

Reexamination Certificate

active

06560142

ABSTRACT:

BACKGROUND OF INVENTION
This invention relates to a capacitorless dynamic random access memory (DRAM) gain cell. In particular, it relates to a self-amplifying large-scale DRAM memory cell that has ultra-high integration density, two field effect transistors, and requires no charge storage capacitor.
The continuing movement of integrated circuit technology toward smaller scales is making system level integration on a chip both possible and desirable. A system level integration generally merges, on a single chip, memory and logic functions. DRAM cells are attractive for such merged system integrations because DRAM cells occupy a small area, and thereby potentially allow a large number of memory cells to be integrated with logic functions. However, even with DRAMs, merging memory and logic involves problems with process complexity and cost. For example, merging conventional DRAMs with logic, using either stacked or trench capacitor cells, is very complex and costly for several reasons. One reason is that logic is frequently performance driven and, when seeking a compromise between cost and performance, the latter may be favored. DRAMs, on the other hand, are frequently cost driven due, in large part, to the sheer number of such devices used in many commercial systems. Another reason is that deep trench technology, as used for DRAM cells, is not preferred for implementing logic. Still another reason is that stacked capacitor technology, which is a conventional DRAM technology, causes problems with the lithography of standard logic processes, due to its non-planar topography.
One possible solution is to use static random access memories (SRAMs), which can be easily integrated with complementary metal oxide semiconductor (CMOS) logic. SRAM cells, however, are not area efficient. Thus, there is a need for a memory cell that occupies a very small area, yet does not require extra processing for integration with the logic, especially large capacitor.
SUMMARY OF INVENTION
An object of the present invention is to provide a high performance, area-efficient memory cell that can be fabricated by conventional CMOS technology, without the need for special process or structural modifications. Moreover, an object of the present invention is to avoid either stacked capacitor or deep trench storage and, instead, to employ standard devices available in high performance CMOS logic technology.
Another object of the invention is to provide a high performance, area-efficient memory cell that can use conventional CMOS voltage levels, thereby facilitating merged system level integration.
Pursuant to these and other objectives, one embodiment of the present invention comprises a storage metal oxide semiconductor field effect transistor (MOSFET), which stores information, and an access MOSFET, which controls the charging and discharging of the gate of the storage MOSFET for writing information. The access MOSFET turns on in response to a write control signal connected to its gate. When the access MOSFET is turned on, a write information signal, representing either a logical “0” or logical “1,” passes through that access MOSFET to the gate of the storage MOSFET. The storage MOSFET is thereby charged to a weak inversion condition or to a depletion (or even majority carrier accumulated) condition in accordance with the write information signal.
To read information, the access MOSFET is turned off and the storage MOSFET is “off-state” because in weak inversion and depletion conditions a conductive channel is not induced at the surface of the storage MOSFET so a current does not flow across the channel. A read control signal connected to the body of the storage MOSFET is applied with a forward bias to the source. The resulting drain current of the storage MOSFET depends upon its gate charge condition, thereby indicating the state of the stored information.
A significant and novel feature of the present invention is that when the storage MOSFET is in a weak inversion charge state, the forward bias of the body at the source junction causes a large bipolar drain current. A current gain for bipolar action depends on the condition of the surface of the body. In a weak inversion condition, the current gain is larger than it is in the depletion condition.
A further embodiment of the present invention is using a different type of MOSFET for the access MOSFET and the stored MOSFET. This results in a one word line and a one bit line circuit.
Yet a further embodiment of the present invention is a method of operating a MOSFET where a constant voltage below but close to the threshold voltage is applied to the gate to place its surface in a depletion or a weak inversion condition and to input a forward signal bias from the body to the source junction, which causes a large bipolar drain current. A current gain for bipolar action depends on the forward signal current.


REFERENCES:
patent: 5784311 (1998-07-01), Assaderaghi et al.
patent: 6111778 (2000-08-01), MacDonald et al.

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