Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-12-13
2004-08-31
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S680000, C438S778000, C438S762000, C438S769000, C438S786000, C438S787000, C438S785000, C257S309000, C257S296000, C257S303000, C257S306000, C257S310000, C257S639000, C257S640000
Reexamination Certificate
active
06784100
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a capacitor and a method for manufacturing of the same.
DESCRIPTION OF THE PRIOR ART
With higher integration of a semiconductor device such as DRAM, dielectric materials having a high dielectric constant are widely used in order to increase a capacitance. Generally, as the dielectric materials, metallic oxide materials such as Ta
2
O
5
, TiO
2
, TaON, HfO
2
, Al
2
O
3
, ZrO
2
, etc., have been developed.
In high integrated devices of 256M or higher DRAM, a tantalum oxide (Ta
2
O
5
) layer used as the dielectric material of capacitors contained in a memory cell has a dielectric constant of about 25, which is 3 times to 4 times as high as a stack dielectric layer i.e., Si
3
N
4
(=~7)/SiO
2
(=~3.8) of a silicon oxide layer and a silicon nitride layer, which is typically used.
FIG. 1
is a cross-sectional diagram showing a schematic structure of a conventional cylinder-type MIS capacitor, in which a tantalum oxide layer as a dielectric layer is applied thereto.
Referring to
FIG. 1
, there is provided a semiconductor substrate
11
on which a transistor (not shown) and a bit line (not shown) are formed. An intermediate insulating layer
12
is formed on the semiconductor substrate
11
. A storage node contact
13
passes through the intermediate insulating layer
12
and is connected to the semiconductor substrate
11
. A cylinder-type lower electrode
14
formed of a polysilicon layer is connected to the storage node contact
13
.
Then, a tantalum oxide layer
15
having a high dielectric constant is formed on the cylinder-type lower electrode
14
, and an upper electrode
16
is formed on the tantalum oxide layer
15
.
However, the MIS capacitor shown in
FIG. 1
has several problems when it is applied to an actual capacitor structure.
For example, when following thermal processes are performed in order to secure a dielectric constant of the tantalum oxide (Ta
2
O
5
) layer, a low dielectric layer such as a silicon oxide layer is formed through an interfacial reaction between the lower electrode and the tantalum oxide layer, so that a total capacitance is remarkably lowered.
Typically, a following thermal process of the tantalum oxide (Ta
2
O
5
) layer is carried out through a plasma process of an oxygen atmosphere, a low-temperature thermal process of UV—O
3
, a thermal process using a furnace, or a high-temperature thermal process of a rapid thermal process. In general, with an advance of the following process, the dielectric characteristic of the tantalum oxide (Ta
2
O
5
) layer itself may be improved. However, oxygen existing within the tantalum oxide layer or oxygen imported during following processes is diffused into the lower electrode to thereby oxidize the lower electrode. Consequently, the dielectric constant of the total dielectric layer will be reduced and the capacitance will be also decreased.
To prevent the oxidation of the lower electrode, an oxidation barrier layer is formed using a rapid thermal nitridation (RTN) of an NH
3
atmosphere, a surface nitridation method through a plasma process of an NH
3
atmosphere, or a deposition method of depositing a silicon nitride (Si
3
N
4
) layer.
FIG. 2
is a cross-sectional diagram explaining a manufacturing process of the oxidation barrier layer according to a conventional surface nitridation method.
Referring to
FIG. 2
, a lower electrode composed of a polysilicon layer
14
is formed, and then a nitridation layer
17
a
is formed on a surface of the polysilicon layer
14
using the nitridation method, such as the rapid thermal nitridation or the plasma process of the NH
3
atmosphere. At this time, the nitridation layer
17
a
formed by the nitridation of the surface of the polysilicon layer
14
is a silicon nitridation (Si
x
N
y
) layer and used as the oxidation barrier layer at the thermal process for securing the dielectric characteristic of a following tantalum oxide layer.
Then, a tantalum oxide layer
15
is deposited on the nitridation layer
17
a
, and a thermal process of an O
2
or N
2
O atmosphere is performed in order to crystallize the tantalum oxide layer
15
and reduce an impurity or an oxygen depletion.
However, the nitridation layer
17
a
which is formed using the surface nitridation method in order for an oxidation resistance is a layer formed by nitrifying only the surface of the polysilicon layer
14
acting as the lower electrode, and the lower electrode
14
is oxidized because the permeation of oxygen is not prevented sufficiently at the thermal process for securing the dielectric characteristic of the tantalum oxide layer
15
.
FIG. 3
is a cross-sectional diagram showing a problem caused when the nitride layer for the oxidation resistance is formed on the lower electrode according to the conventional deposition method, in which a silicon nitride layer is unevenly formed along a lower layer.
Referring to
FIG. 3
, a storage node contact
13
is formed within an intermediate insulating layer
12
and connected to a semiconductor substrate (not shown). A lower electrode composed of a polysilicon layer
14
is formed on the storage node contact
13
. Sequentially, a silicon nitride layer
17
b
is deposited on the polysilicon layer
14
using the deposition method. Thereafter, a tantalum oxide layer
15
is deposited on the silicon nitride layer
17
b
and a thermal process of an O
2
, O
3
or N
2
O atmosphere is performed in order to secure the dielectric characteristic of the tantalum oxide layer
15
.
Here, the silicon nitride layer
17
b
acting as the oxidation barrier layer formed according to the deposition method must have a thickness of 50 Å or less in order to secure the dielectric characteristic thereof.
However, since the lower layers exposed prior to the deposition of the silicon nitride layer
17
b
is different from each other, there occurs a problem that the silicon nitride layer is unevenly deposited.
In other words, as shown in
FIG. 3
, the cylinder-type lower electrode is connected to the storage node contact
13
passing through the intermediate insulating layer
12
. At this time, when the cylinder-type lower electrode is formed of the polysilicon layer
14
and the silicon nitridation layer
17
b
is deposited on the polysilicon layer
14
, the neighbor intermediate insulating layer
12
as well as the polysilicon layer
14
is exposed prior to the deposition of the silicon nitride layer
17
b
includes.
Accordingly, respective incubation times in the polysilicon layer
14
and, the intermediate insulating layer
12
are different from each other. In other words, a deposition rate of the silicon nitride layer
17
b
is different along the lower layer. As a result, although the silicon nitridation layer
17
b
is deposited on the polysilicon layer
14
to a desired thickness, it is deposited on the intermediate insulating layer
12
to a thin thickness. Therefore, the oxygen is permeated through the interface between the silicon nitride layer
17
b
of a thin thickness and the intermediate insulating layer
12
at the following thermal process, so that the polysilicon layer
14
is oxidized.
Further, an generation and increase of the leakage current of the capacitor will be caused due to the uneven-thickness characteristic of the silicon nitride layer
17
b.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a capacitor which is adaptable for preventing a lower electrode from being oxidized at a following thermal process and a method for manufacturing of the same.
To accomplish the above object, there is provided a capacitor which includes: a lower electrode; an oxide barrier layer formed on the lower electrode, wherein the oxide barrier layer is formed of at least double nitridation layers; a dielectric layer formed on the oxide barrier layer; and an upper electrode formed on the dielectric layer.
Further, to accomplish the above object, there is provided a method for manufacturing
Kim Kyong-Min
Oh Hoon-Jung
Park Jong-Bum
Anya Igwe U.
Hynix / Semiconductor Inc.
LandOfFree
Capacitor with oxidation barrier layer and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Capacitor with oxidation barrier layer and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Capacitor with oxidation barrier layer and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3305107