Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-26
2001-12-25
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S310000
Reexamination Certificate
active
06333529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device and, more particularly, a semiconductor device and a method of manufacturing a semiconductor device I including steps of fabricating a capacitor.
2. Description of the Prior Art
There is an FeRAM (Ferroelectric Random Access Memory) as the nonvolatile semiconductor memory device. The FeRAM comprises a capacitor having a high-ferroelectric film and a memory cell formed of an n-type MOS transistor. As such high-ferroelectric material, PZT, PLZT, etc. which have a perovskite structure, for example, are employed. Such high-ferroelectric film is formed by the sputtering method, the CVD method, the sol-gel process, etc. Since the high-ferroelectric film must be oxidized and crystallized in the high-temperature oxygen atmosphere, platinum (Pt), ruthenium (Ru), iridium (Ir), or the like, which is difficult to be oxidized or which does not lose conductive property even if oxidized, is employed as electrode material.
PZT is short for lead zirconate titanate (Pb(Zr
x
Ti
1−x
)O
3
). PLZT is PZT in which lanthanum is added, and its chemical formula is Pb
y
La
1−y
(Zr
x
Ti
1−x
)O
3
.
By way of example, the semiconductor memory device employing the high-ferroelectric capacitor is manufactured by the steps described in the following.
First, as shown in
FIG. 1A
, an n-type MOS transistor
2
is formed on a silicon substrate
1
. The n-type MOS transistor
2
is formed in a region which is surrounded by a device isolation insulating layer
6
on a surface of the silicon substrate
1
. The n-type MOS transistor
2
comprises a gate electrode which is formed on the silicon substrate
1
via a gate insulating film
3
, and a source region
5
s
and a drain region
5
d
which are formed in the silicon substrate
1
on both sides of the gate electrode
4
.
The gate electrode
4
constitutes a part of a word line WL, and remaining portion of the word line WL is positioned to pass through on the device isolation insulating layer
6
.
After the n-type MOS transistor
2
and the word line WL have been formed, an interlayer insulating film
7
is formed to cover the n-type MOS transistor
2
, the word line WL, etc., as shown in FIG.
1
B.
Then, steps needed until a configuration shown in
FIG. 1C
is formed will be explained hereunder.
A first platinum (Pt) layer
8
and a PZT layer
9
are then grown in sequence on the interlayer insulating film
7
over the device isolation insulating layer
6
which is formed adjacent to the n-type MOS transistor
2
. A resultant structure is then annealed in the oxygen atmosphere to crystallize the PZT layer
9
. A second platinum layer
10
is then formed on the PZT layer
9
.
After this, the second platinum layer
10
is patterned by using the photolithography technology which employs an etching gas and a resist mask. The patterned second platinum layer
10
is employed as an upper electrode of the capacitor.
The PZT layer
9
is then patterned by using the photolithography technology to shape a dielectric layer of the capacitor. A lower electrode of the capacitor is then formed by patterning the first platinum layer
8
by using the photolithography technology.
With the above, patterning of the capacitor has been completed.
A protection insulating film
11
formed of SiO
2
is then grown on an overall surface by the chemical vapor deposition using TEOS (Tetraethoxysilane). As shown in
FIG. 1D
, a first opening portion
11
a
and a second opening portion
11
b
are then formed by patterning the protection insulating film
11
such that the second platinum layer (upper electrode)
10
is exposed from the first opening portion
11
a
and also the first platinum layer (lower electrode)
8
is exposed from the second opening portion
11
b.
As shown in
FIG. 1E
, a third opening portion
11
g
, a fourth opening portion
11
d
, and a fifth opening portion
11
s
are then formed by patterning the protection insulating film
11
and the interlayer insulating film
7
to expose the gate electrode (word line WL), the drain region
5
d
, and the source region
5
s
respectively.
In turn, an aluminum layer is formed on an overall surface. As shown in
FIG. 1F
, wirings
12
a
,
12
b
,
12
s
,
12
d
,
12
g
made of aluminum are then formed by patterning the aluminum layer by using the photolithography.
The above steps have been set forth in Patent Application Publication (KOKAI) hei 8-37282, for example, etc.
In the semiconductor memory device having the above-mentioned configuration, the capacitor is heated and exposed to the reduction atmosphere inevitably in the step of forming the protection insulating film
11
, the step of forming the opening portions
11
a
,
11
b
, etc. to reduce residual polarization charge in the PZT layer
9
. Therefore, electric characteristics of the capacitor are degraded.
The upper electrode
10
is ready to peel if it is subjected to the step of forming the protection insulating film
11
and various subsequent steps.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of manufacturing a semiconductor device which is capable of preventing peeling of an upper electrode and thus improving electric characteristics of a capacitor.
In order to achieve the above object, there is provided a semiconductor device comprising a capacitor, wherein the capacitor includes a lower electrode, a dielectric oxide film formed on the lower electrode, and an upper electrode formed on the dielectric oxide film and formed of at least a noble metal containing oxygen having a concentration of more than 1×10
20
atoms/cm
3
.
In order to achieve the above object, there is provided a method of manufacturing a semiconductor device comprising the steps of forming an insulating film over a semiconductor substrate; forming a lower electrode on the insulating film; forming a dielectric oxide film on the lower electrode; forming an upper electrode made of at least a noble metal on the dielectric oxide film; patterning the lower electrode, the dielectric oxide film, and the upper electrode; covering the lower electrode, the dielectric oxide film, and the upper electrode with an insulating protection film; forming an opening by patterning the insulating protection film to expose at least a part of the upper electrode; and supplying an oxygen to the upper electrode and the dielectric oxide film via the opening to set a concentration of oxygen contained in the upper electrode to 1×10
20
atoms/cm
3
or more.
According to the present invention, the upper electrode is formed on the dielectric oxide film and made of at least a noble metal such as platinum, iridium, etc., and the oxygen concentration contained in the upper electrode is set to more than 1×10
20
atoms/cm
3
.
Accordingly, it has been confirmed based on the experiment that the upper electrode becomes difficult to peel from the dielectric oxide film.
In this case, if the oxygen concentration in the dielectric oxide film is set to 5×10
19
toms/cm
3
, residual polarization charge to stabilize an operation of the FeRAM can be achieved.
Adjustment of the oxygen concentration can be performed by annealing the structure in the oxygen containing atmosphere after the capacitor having the dielectric oxide film is formed and then the electrode connecting opening portion is formed in the protection film.
REFERENCES:
patent: 5555486 (1996-09-01), Kingon et al.
patent: 5864153 (1999-01-01), Nagel et al.
patent: 5905278 (1999-05-01), Nakabayashi
patent: 5929475 (1999-07-01), Uemoto et al.
patent: 5973911 (1999-10-01), Nishioka
patent: 5-343616 (1993-12-01), None
patent: 7-263570 (1995-10-01), None
patent: 8-55967 (1996-02-01), None
patent: 08-037282 (1996-02-01), None
patent: 8-274270 (1996-10-01), None
patent: 9-64291 (1997-03-01), None
Ashida Hiroshi
Tomotani Miki
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Loke Steven
Owens Douglas W.
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