Capacitor with high charge storage capacity

Details Capacitor with high charge storage capacity Capacitor with high charge storage capacity

1999-04-29

2004-03-02

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S301000, C257S303000, C257S306000, C257S310000

Reexamination Certificate

active

06700145

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electrical circuits and their components. More particularly, this invention relates to a thin-film capacitor characterized by a high charge storage capacity achieved by a combination of a high-dielectric constant insulator and either high-dielectric constant electrodes or superconducting electrodes.
2. Description of the Prior Art
Capacitors are typically formed to have a metal/insulator/metal structure (where “metal” here means any highly-conductive electrode material). The capacitance per unit area of a parallel-plate capacitor is well described by:
C
=∈
0
∈
F
/t
where ∈
0
is the permittivity of free-space (a physical constant), ∈
F
is the dielectric constant of the insulator, and t is the insulator thickness. Thin-film capacitors of the type used for high-density applications such as DRAM (dynamic random access memory) typically use thin (t≈5 nm) combinations of silicon dioxide (Si0
2
) and silicon nitride (S
3
N
4
) as insulators, with an effective dielectric constant (∈
F
) of about 5, yielding a capacitance on the order of about 1.5 to 2 fF/&mgr;m
2
. As memory densities increase, it becomes increasingly difficult to store adequate charge in ever-decreasing memory cell areas. As an example, for a one Gigabit (Gb) DRAM, the amount of planar area available for the capacitor in a memory cell may be on the order of only 0.05 &mgr;m
2
. Consequently, to obtain capacitances on the order of 30 fF, it has become necessary to build highly-complicated, three-dimensional capacitors to increase the available interface surface area between the insulator and electrodes. The two main types are trench capacitors, which require deep, narrow holes in the substrate (typically silicon) on which the capacitors are formed, and stack capacitors which require tall, thin electrodes built above the substrate. Both types are becoming very difficult and expensive to build, due to the high aspect ratios involved.
In order to reduce the size of these capacitor structures, extremely high-capacity capacitors (on the order of 300 fF/&mgr;m
2
or more) would be advantageous. In the past, capacitance density has been primarily increased by reducing the insulator thickness t. However, as thickness is reduced, prohibitively large leakage currents can occur. Thus, intensive research has begun into the development of what has been termed “high-dielectric constant” insulators, such as barium strontium titanate (Ba
x
Sr
1−x
TiO
3
; BST), which have dielectric constants on the order of 500 to 1000. From the equation above, the capacitance is proportional to the dielectric constant and inversely proportional to the insulator thickness. As a result, a BST capacitor (∈
F
=500 to 1000) would be expected to have at least 100 times the capacitance density of a silicon dioxide capacitor (∈
F
=about 5) of identical insulator thickness. However, experimentally it has been found that the effective dielectric constant of a BST capacitor drops precipitously as its thickness is decreased, greatly limiting the actual capacitance that is achievable. While a portion of this decrease is undoubtedly due to variable quality of the BST thin film, a large portion is attributable to the interfaces between the insulator and metal electrodes. More specifically, a series capacitor is formed if there is any additional material layer (e.g., surface oxide or residual chemical scum) left at one or both of the insulator/electrode interfaces, or if the crystal structures of the insulator and electrodes are such that a transition layer or “dead” layer forms at one or both interfaces, i.e., if there is any layer between an electrode and the insulator which is neither fully-conducting like the electrode, nor has the high-dielectric constant of the insulator. Under such circumstances, the overall capacitance of the capacitor structure is:
1
/C
eff
=1
/C
insulator
+1
/C
interfaces
Since the capacitances add reciprocally, the overall capacitance is reduced by the presence of an interface layer. Further, since the interface capacitance is often much smaller than a high-dielectric insulator such as BST, the reduction in capacitance can be quite large. As the insulator becomes thinner, C
insulator
approaches infinity, so the capacitance C
eff
is dominated by, and eventually will become equal to, the interface capacitance. Consequently, the effect of the interface layer is believed to explain the decrease in capacitance observed when capacitors with high-dielectric insulators are scaled for DRAM applications.
Several approaches have been tried to mediate this interface capacitance issue. One such approach has been to improve processing and cleaning steps to achieve a more abrupt, clean interface. In addition, it has been recognized that the choice of electrode metals can have a significant effect. In particular, platinum (Pt) is a popular choice because it is highly resistant to surface oxide formation. Another approach has been to use conductive oxides, such as iridium dioxide (IrO
2
), as the electrode material, again preventing the formation of any barrier
onconducting interface oxide. Finally, electrode materials with perovskite crystal structures (“perovskite materials”), which may have stoichiometry ABO
3
(where A is an element such as calcium, strontium or barium, and B is an element such as ruthenium or titanium), have been evaluated. These perovskite electrode materials have been used with high-dielectric perovskite insulator materials, such as BST, with the expectation that the interface between insulator and electrode materials of the same (perovskite) crystal structure might reduce interface capacitance.
Though the approaches described above have met some success, none have yet eliminated the detrimental effect attributed to the presence of an insulator/electrode interface layer. Accordingly, there is a need for further improvements in capacitances of thin-film capacitors, and particularly those having limited available planar surface area.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a capacitor structure characterized by improved capacitance as a result of increasing the capacitance associated with charge spreading that occurs within the electrodes of the capacitor. Because this capacitance adds in series with the insulator capacitance, increasing the electrode capacitance is able to have a significant affect on the overall capacitance of the capacitor, particularly if the capacitor insulator is formed of a thin-film high-dielectric material.
Capacitors in accordance with this invention generally have an insulator between a pair of electrodes, with at least one of the electrodes being formed of a material that is either superconducting or has a high dielectric constant, preferably on the order of at least 10. To maximize the capacitance of the capacitor, the insulator is preferably formed of a high-dielectric constant material, preferably a dielectric constant of at least 20. Notably, improvements in capacitance can be achieved with this invention though the electrodes might have a crystal structure that is dissimilar to that of the insulator, including the situation where both the electrode and insulator materials have perovskite crystal structures but different lattice constants. In addition, either or both the electrodes and insulator may have a non-perovskite crystal structure. Accordingly, the present invention is contrary to the generally-accepted rationale behind the prior use of certain perovskite electrode materials with certain high-dielectric perovskite insulator materials, which was based on the belief that crystal lattice matching was required to reduce interface capacitance.
In view of the above, it can be seen that, while prior art attempts to increase the capacitance of thin-film capacitors, such as large memory DRAM with limited available planar surface area, have been directed toward reducing the extrinsic por

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