Capacitor structures for dynamic random access memory cells

Details Capacitor structures for dynamic random access memory cells Capacitor structures for dynamic random access memory cells

1993-11-15

1996-02-13

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257309, 257534, 437 48, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

054913560

ABSTRACT:
A three dimensional capacitor structure particularly adapted for use as a memory cell capacitor of a DRAM is disclosed. The capacitor structure incorporates the substantially vertical (in relation to the substrate) sides of a plurality of spacers into the storage node capacitor to increase the total area of the storage node capacitor. In the described embodiments of the invention, a first spacer and a second spacer are formed next to the digit lines. The bottom storage node plate is formed on at least the first sides of the spacers to increase area of the storage node. The bottom storage node plate is also formed on the upper surface of the digit line. Additional spacers can also be added to further increase the area of the storage node. A dielectric layer is formed over the first capacitor plate and a second capacitor plate layer is formed over the dielectric layer to complete the structure.

REFERENCES:
patent: 4754313 (1988-06-01), Takemae et al.
patent: 4951175 (1990-08-01), Kurosawa et al.
patent: 5045899 (1991-09-01), Arimoto
patent: 5059548 (1991-10-01), Kim
patent: 5172201 (1992-12-01), Suizu
S. Inque, et al., "A Spread Stacked Capacitor (SSC) Cell for 64 Mbit DRAMs," ULSI Research Center, Toshiba Corporation, 1, Komukai Toshiba-cho, Saiwai-ku, Kawasaki 210, Japan, IUEDM 89-31, p. 2.3.1.
T. Ema, et al, "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs," MOS Division, Fujitsu Limited SKawasaki, Japan, Fujitsu Laboratories Limited, Atsugi, Japan, 592-IDEM 88.

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