Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-23
2004-04-06
Lee, Eddie (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S307000
Reexamination Certificate
active
06717201
ABSTRACT:
TECHNICAL FIELD
This invention relates to capacitors, dynamic random access memory (DRAM) circuitry, to methods of forming capacitors, and to methods of forming DRAM circuitry.
BACKGROUND OF THE INVENTION
As integrated circuitry increases in density, there is a continuing challenge to maintain sufficiently high storage capacitances for storage capacitors despite decreasing circuitry dimensions. In particular, as DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell areas. Additionally, there is a continuing goal to further decrease cell areas. One principle way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trench or stacked capacitors.
This invention arose out of concerns associated with improving capacitor storage capabilities through improved structures and formation techniques.
SUMMARY OF THE INVENTION
Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.
REFERENCES:
patent: 5408114 (1995-04-01), Sakao
patent: 5468670 (1995-11-01), Ryou
patent: 5476805 (1995-12-01), Woo et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5506166 (1996-04-01), Sandhu et al.
patent: 5512768 (1996-04-01), Lur et al.
patent: 5804852 (1998-09-01), Yang et al.
patent: 5835337 (1998-11-01), Watanabe et al.
patent: 5872041 (1999-02-01), Lee et al.
patent: 5933742 (1999-08-01), Wu
patent: 5939747 (1999-08-01), Yajima
patent: 6002574 (1999-12-01), Metzler et al.
patent: 6031262 (2000-02-01), Sakao
patent: 6051464 (2000-04-01), Chen et al.
patent: 6259125 (2001-07-01), Fazan et al.
patent: 6259127 (2001-07-01), Pan
patent: 6323081 (2001-11-01), Marsh
patent: 004213945 (1992-11-01), None
Pierrat Christophe
Roberts Martin Ceredig
Lee Eddie
Micro)n Technology, Inc.
Owens Douglas W.
Wells St. John P.S.
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