Capacitor structure

Details Capacitor structure Capacitor structure

1999-04-01

2002-10-01

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S308000, C257S309000, C257S307000

Reexamination Certificate

active

06459116

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention is directed to the fabrication of microelectronic storage devices. In particular the present invention is concerned with methods of making a concave shaped capacitor in a stacked capacitor memory device such as a dynamic random-access memory (DRAM) where a large ratio of surface area to capacitor volume is desired.
2. The Relevant Technology
In fabrication of microelectronic devices there exists a relentless pressure to continue miniaturization for higher device density on a single chip and to increase device speed and reliability. It is advantageous to form integrated circuits with smaller individual elements so that as many elements as possible may be formed in a single chip. In this way, electronic equipment becomes smaller and more reliable, assembly and packaging costs are minimized, and integrated circuit performance is improved. One device that is subject to the ever-increasing pressure to miniaturize is the DRAM. DRAMs comprise arrays of memory cells that contain two basic components—a field effect access transistor and a capacitor. Typically, one side of the transistor is connected to one side of the capacitor. The other side of the transistor and the transistor gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other side of the capacitor is connected to a reference voltage. Therefore, the formation of the DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to external circuits. The DRAM has one MOS transistor and one capacitor within a semiconductor substrate on which a plurality of spaced gates, that is, word lines, and a plurality of spaced metal wires, that is, bit lines are aligned perpendicular to each other in width-wise and lengthwise directions. Additionally, one capacitor having a contact hole in the center thereof is formed for every two gates and extends across the bit lines.
The recent trend of high integration of semiconductor devices, especially DRAM devices, has been based on the diminution of the capacitor storage cell, which leads to difficulty in providing a capacitor with sufficient capacitance to hold a charge long enough between refreshes for an optimally desired length of time.
The capacitor is usually the largest element of the integrated circuit chip. Consequently, the development of smaller DRAMs focuses to a large extent on the capacitor. Three basic types of capacitors are used in DRAMs—planar capacitors, trench capacitors, and stacked capacitors. Most large capacity DRAMs use stacked capacitors because of their greater capacitance, reliability, and ease of formation. For stacked capacitors, the side of the capacitor connected to the transistor is commonly referred to as the storage node, and the side of the capacitor connected to the reference voltage is called the cell plate. The cell plate is a layer that covers the entire top array of all the substrate-connected devices, and the storage node is compartmentalized for each respective bit storage site.
In a stacked capacitor, a conductor is usually made mainly of polysilicon, and a dielectric material is selected from a group consisting broadly of an oxide, a nitride and an oxide-nitride-oxide (ONO) laminator. In general, a capacitor occupies a large area on a semiconductor chip. Accordingly, it is one of the most important factors for high integration of DRAM devices to reduce the size of the capacitor yet to maintain the capacitance thereof.
The capacitance of a capacitor is represented by C=(&kgr;∈
o
A)/T where C is capacitance, ∈
o
is permitivity of vacuum, &kgr; is the dielectric constant of the dielectric layer, A is the surface area of the capacitor, and T is the thickness of dielectric layer. The equation illustrates that the capacitance can be increased by employing dielectric materials with high dielectric constants, making the dielectric layer thin, and increasing the surface area of the capacitor.
The areas in a DRAM to which electrical connections are made are generally referred to as active areas. Active areas, which serve as source and drain regions for transistors, are discrete specially doped regions in the surface of the silicon substrate.
The ever-increasing pressure to miniaturize has placed capacitors of DRAMs under the strain of becoming ever smaller without losing the ability to hold a sufficient charge between refreshes. The challenge of making a capacitor that can hold a charge between refreshes can be approached by a larger capacitor surface area in a smaller space, or by insulating the capacitor to resist significant charge bleed-off between refreshes.
A need exists in the art for a capacitor that is contained in a small total volume that optimizes the surface area for charge storage, which capacitor is fabricated without costly and difficult extra processing steps.
SUMMARY OF THE INVENTION
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term “semiconductor substrate” is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductor wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductor substrates described above.
The present invention is directed to fabrication of capacitors that have concave shapes and optional convoluted surfaces in order to optimize surface area in a confined volume. The capacitors are fabricated in microelectronic fashion in order to make dense DRAM arrays. Capacitors that hold significant charges for a given volume assist in increased miniaturization efforts in the microelectronic field where a significant charge is stored in a smaller volume.
Methods of fabrication include stack building with storage nodes that extend both above the semiconductor substrate surface in some embodiments of the inventive method, and above and below the semiconductor substrate in others. Isolation trenches are included in the manufacturing methods in order to resist charge bleed off between refreshes.
The first twelve embodiments of the present inventive method are methods of stacked capacitor formation in which a polysilicon plug between gate stacks forms part of the structure. The thirteenth through twentieth embodiments of the inventive method are methods of stacked capacitor formation with no polysilicon plug between the gate stacks.
A preferable aspect to each of the first through the twentieth embodiment of the inventive method is that each said embodiment requires only a single masking step in the formation of the concave storage container cell into which a capacitor is formed.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.


REFERENCES:
patent: 5300801 (1994-04-01), Blalock et al.
patent: 5478769 (1995-12-01), Lim
patent: 5478770 (1995-12-01), Kim
patent: 5679598 (1997-10-01), Yee
patent: 5686337 (1997-11-01), Koh et al.
patent: 5952687 (1999-09-01), Kawakubo et al.
patent: 5962885 (1999-10-01), Fischer et al.

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