Semiconductor device manufacturing: process – Making passive device – Planar capacitor
Reexamination Certificate
2000-05-02
2002-01-15
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Planar capacitor
C257S303000
Reexamination Certificate
active
06339007
ABSTRACT:
DESCRIPTION
1. Technical Field
The present invention relates to capacitors and more particularly to a stacked capacitor. The capacitors of the present invention are especially suitable for high density dynamic random-access memory devices (DRAM). The capacitors of the present invention comprise a recessed electrode structure. The present invention also relates to methods of fabricating the capacitors of the present invention.
2. Background of Invention
Capacitors are widely used in integrated circuit devices such as Dynamic Random Access Memory (DRAM) devices. As DRAM devices become more highly integrated, various approaches for increasing the capacitance within a defined cell area have been proposed.
It has been reported that the density of dynamic random-access memory (DRAM) has increased by a factor of 4x every three years during the past 25 years, and this trend continues today. This remarkable increase in density has been brought about by advances in various areas of technology, including lithography, dry patterning, and thin-film deposition techniques, and by improvements in the DRAM architecture resulting in a more efficient cell utilization.
Since DRAM cells contain a single transistor and capacitor and each capacitor must be isolated from adjacent capacitors in the array, only a fraction of the cell area can be occupied by the capacitor.
Higher capacitance density can be achieved by the use of 1) complex electrode structures providing a large surface area within a small lateral area; 2) thinner capacitor dielectrics; and 3) higher-permittivity capacitor dielectric materials. In general, increasing the surface area leads to increased complexity and hence increased cost.
The commonly used silicon dioxide and silicon nitride dielectrics suffer from limitations of their required thicknesses. Accordingly, significant work in recent years has focused on the development of high-permittivity materials for a DRAM capacitor. DRAM chips manufactured to date contain primarily capacitors utilizing a thin dielectric containing a mixture of silicon dioxide and silicon nitride sandwiched between two electrodes made of doped crystalline or polycrystalline silicon. Incorporating a high-permittivity material into a DRAM capacitor drives the need not only for new dielectric materials, but also for new electrode and barrier materials. Thin-film barium-strontium titanate (Ba, Sr) TiO
3
(BSTO), with a permittivity in the range 200-350 and a specific capacitance exceeding 125 fF/&mgr;m
2
, has been proposed as the leading contender as a dielectric for future DRAMs.
Furthermore, the contact barrier of high dielectric stack capacitors is critical for future generations of DRAM. Currently, the contact barrier used is a TaSiN barrier layer.
A typical structure of a stack capacitor is shown in
FIG. 1
wherein
1
represents a lower platinum electrode,
2
represents the TaSiN barrier layer between platinum electrode
1
and plug
3
such as polycrystalline silicon. The dielectric
4
comprises Ba
0.7
/Sr
0.3
TiO
3
(BSTO). An upper platinum electrode (not shown) will be stacked above lower platinum electrode and BSTO layer
4
.
However, during the BSTO deposition, which is carried out in an oxygen environment, TaO and/or SiO is formed at the top of the TaSiN layer. This results in a resistive layer between the Pt and TaSiN, which has a lower capacitance than the BSTO material. There exists two sources of O diffusion. One is from the sidewall as indicated in
FIGS. 1
at
6
, and the other is from the grain Pt grain boundaries. The sidewall oxygen diffusion can be solved by making a recessed barrier structure, however, the Pt grain boundary problem is not readily abrogated.
SUMMARY OF INVENTION
The present invention addresses the problem of oxygen diffusion through the electrode. The present invention provides a recessed electrode structure which interrupts the grain boundaries of the electrode while also protecting against side wall diffusion.
More particularly, the present invention relates to a capacitor structure which comprises a top electrode and a bottom electrode, wherein the bottom electrode is from depositing a first electrode portion which is recessed with respect to electric insulator on the sidewalls thereof and depositing a second electrode portion; and wherein dielectric is present on the sidewalls and top of the second electrode portion of the bottom electrode; and wherein the top electrode is located above the dielectric.
A further aspect of the present invention relates to a semiconductor structure which comprises the above-disclosed capacitor structure located above a conductive plug and a barrier layer located between the conductive plug and capacitor structure.
A still further aspect of the present invention relates to a semiconductor structure which comprises the capacitor structure disclosed above located above an electrode contact line and a conductive plug in contact with the electrode contact line.
The present invention also relates to a method for fabricating an electrode for a capacitor structure. The method comprises depositing a first electrode layer onto a surface,
depositing a protective layer on top of the first electrode layer to form a stacked structure;
patterning the stacked structure;
depositing and polishing electrical insulator layer to provide insulator on the sidewalls of the stacked structure;
removing the protective layer by etching;
recessing the first electrode layer with respect to the electrical insulator;
depositing a second electrode layer on top of the first electrode layer and patterning the second electrode layer; and
depositing a dielectric layer on top of and on the sidewalls of the second electrode layer.
A still further aspect of the present invention is concerned with an electrode obtained by the above-disclosed process.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
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patent: 5585998 (1996-12-01), Kotecki et al.
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patent: 5696015 (1997-12-01), Hwang
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patent: 5825609 (1998-10-01), Andricacos et al.
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Kotecki et al, (Ba,Sr) TiO3dielectrics for furture stacked-capacitor DRAM,IBM J. Res. Develop., vol. 43, No. 3, May 1999: 367-382.
Jammy Rajarao
Kimball Lee J.
Kotecki David E.
Lian Jenny
Lin Chenting
Connolly Bove Lodge & Hutz
Hoang Quoc
Nelms David
Schnurmann H. Daniel
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