Redundancy circuitry for programmable logic devices with...

Details Redundancy circuitry for programmable logic devices with... Redundancy circuitry for programmable logic devices with...

2001-02-28

2002-01-08

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S041000

Reexamination Certificate

active

06337578

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic devices, and more particularly, to redundancy circuitry for repairing programmable logic devices containing defects.
Programmable logic devices are integrated circuits that may be programmed to perform custom logic functions. Integrated circuit fabrication techniques are not perfect, so occasionally a programmable logic device may be fabricated with a defect. Unless the defect can be repaired before the logic device is put into use, the logic device must be discarded. Discarding such a device is wasteful, particularly when a defect is relatively minor. As a result, various redundancy schemes have been developed that allow spare circuitry to be switched into place to repair a defective portion of a circuit.
The difficulty of implementing a suitable redundancy scheme for a given logic device architecture depends on the attributes of the architecture. For example, there are difficulties associated with providing redundancy for programmable logic devices that use interleaved multiplexer circuitry to distribute signals to logic array blocks. Because adjacent logic array blocks share signal routing resources in such arrangements, the occurrence of a defect in one logic array block can affect an adjacent and otherwise defect-free logic array block. Although it might be possible to use a redundancy scheme in which both of these affected logic array blocks are replaced upon detection of a defect, such a scheme would necessarily involve bypassing at least one defect-free logic array block. A redundancy scheme that uses logic resources more efficiently would be desirable.
It is therefore an object of the present invention to provide a redundancy arrangement for programmable logic devices with interleaved input circuits.
SUMMARY OF THE INVENTION
This and other objects of the invention are accomplished in accordance with the principles of the present invention by providing redundant circuitry for a programmable logic device that uses interleaved input multiplexer circuits to distribute signals to adjacent logic regions. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between logic regions.
Each interleaved input multiplexer circuit distributes logic signals from the conductors in the row to two adjacent logic regions. One of the logic regions to which the signals are distributed is in the same column as the interleaved input multiplexer circuit. The other logic region to which the signals are distributed is in an adjacent column.
Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. During manufacturing of the device, the device is tested to determine if any of the columns contain defective circuitry. If a defect is detected in a column, the manufacturer can repair the device by configuring the bypass circuitry to bypass that column during use of the device.
During programming of the programmable logic device, a user supplies programming data to the device that directs the various logic components on the device to perform desired logical functions. If a column of circuitry contains a defect, circuitry previously configured by the manufacturer shifts the programming data originally intended for that column into an adjacent column. The programming data originally intended for the adjacent column and each successive column of logic in the row is also shifted.
A spare column of logic is provided at the end of the row to receive the shifted programming data from the last column of regular logic when the programming data for the various columns of logic is being shifted to accommodate the bypassing of a defective column. The spare logic makes up for the logic that is lost when the defective column is bypassed. As a result, the same number of logic regions are used regardless of whether the device is repaired following detection of a defect or was defect free initially.
Outputs from the logic regions are applied to the conductors using programmable drivers. The drivers associated with each column typically form a unique pattern of connections to the conductors. When programming data is shifted to a successive column during repair of a defect, the programming data associated with the drivers is also shifted to the successive column. In one arrangement, the programmable logic device uses programming data redirecting circuitry to redirect the shifted programming data for the drivers back to the drivers in the original column. In another arrangement, auxiliary drivers are provided in each column. The auxiliary drivers in each column form the same pattern of connections to the conductors that are formed by the normal drivers in the previous column. When a column containing a defect is repaired, the auxiliary drivers in successive columns are used in place of the normal drivers to ensure that the outputs of the logic regions in the successive columns are directed to the same destinations that they would have been directed to had the programming data not been shifted.
The logic regions are preferably programmable logic array blocks, each of which contains a plurality of programmable logic elements based on a four-input look-up table or based on product term logic.
Two sets of logic array blocks may be provided in a row. In this type of arrangement, a single spare logic array block may be provided in the center of the row. This reduces the overhead associated with redundancy, because the two sets of logic array blocks in the row can share the spare logic array block.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.


REFERENCES:
patent: 33521 (1861-10-01), Mori et al.
patent: 3566153 (1971-02-01), Spencer, Jr. et al.
patent: 3805039 (1974-04-01), Stiffler
patent: 3995261 (1976-11-01), Goldberg
patent: 4020469 (1977-04-01), Manning
patent: 4051354 (1977-09-01), Choate
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4380811 (1983-04-01), Götze et al.
patent: 4538247 (1985-08-01), Venkateswaran
patent: 4551814 (1985-11-01), Moore et al.
patent: 4566102 (1986-01-01), Hefner
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4641285 (1987-02-01), Sasaki et al.
patent: 4677318 (1987-06-01), Veenstra
patent: 4691301 (1987-09-01), Anderson
patent: 4700187 (1987-10-01), Furtek
patent: 4703206 (1987-10-01), Cavlan
patent: 4706216 (1987-11-01), Carter
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4722084 (1988-01-01), Morton
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 4791319 (1988-12-01), Tagami et al.
patent: 4798976 (1989-01-01), Curtin et al.
patent: 4800302 (1989-01-01), Marum
patent: 4829198 (1989-05-01), Maley et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 4920497 (1990-04-01), Upadhyaya et al.
patent: 4928022 (1990-05-01), Marum
patent: 5019736 (1991-05-01), Furtek
patent: 5045720 (1991-09-01), Bae
patent: 5121006 (1992-06-01), Pedersen
patent: 5163023 (1992-11-01), Ferris et al.
patent: 5187393 (1993-02-01), El Gamal et al.
patent: 5204836 (1993-04-01), Reed
patent: 5220214 (1993-06-01), Pedersen
patent: 5237219 (1993-08-01), Cliff
patent: 5255227 (1993-10-01), Haeffele
patent: 5255228 (1993-10-01), Hatta et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5325334 (1994-06-01), Roh et al.
patent: 5369314 (1994-11-01), Patel et al.
patent: 5426379 (1995-06-01), Trimberger
patent: 5434514 (1995-07-01), Cliff et al.
patent: 5459342 (1995-10-01), Nogami et al.
patent: 5471427 (1995-11-01), Murakami et al.
patent: 5483178 (1996-01-01), Costello et al.
patent: 5485102 (1996-01-01), Cliff et

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